公开(公告)号：EP2737396A2

公开(公告)日：2014-06-04

申请号：EP12819390.1

申请日：2012-06-29

申请人： Intel Corporation

发明人： GINZBURG, Boris ,  NATANZON, Esfirush ,  OSADCHIY, Ilya ,  ZACH, Yoav

IPC分类号： G06F9/06 ,  G06F15/163

CPC分类号： G06T1/20 ,  G06T1/60

摘要： A thread on one processor may be used to enable another processor to lock or release a mutex. For example, a central processing unit thread may be used by a graphics processing unit to secure a mutex for a shared memory.

摘要翻译： 可以使用一个处理器上的线程来使另一个处理器能够锁定或释放互斥体。 例如，图形处理单元可以使用中央处理单元线程来保护用于共享存储器的互斥体。

公开(公告)号：EP2684123A1

公开(公告)日：2014-01-15

申请号：EP11861151.6

申请日：2011-12-29

申请人： Intel Corporation

发明人： GINZBURG, Boris ,  NATANZON, Esfir ,  OSADCHIY, Ilya ,  RONEN, Ronny ,  WEISSMANN, Eliezer ,  ZACH, Yoav ,  FARRELL, Robert L.

IPC分类号： G06F9/06 ,  G06F9/30 ,  G06F13/14 ,  G06F12/08

CPC分类号： G06F12/1027 ,  G06F12/1036 ,  G06F12/109 ,  G06F2212/302 ,  G06F2212/682

摘要： Page faults arising in a graphics processing unit may be handled by an operating system running on the central processing unit. In some embodiments, this means that unpinned memory can be used for the graphics processing unit. Using unpinned memory in the graphics processing unit may expand the capabilities of the graphics processing unit in some cases.

公开(公告)号：EP2684123B1

公开(公告)日：2017-02-01

申请号：EP11861151.6

申请日：2011-12-29

申请人： Intel Corporation

发明人： GINZBURG, Boris ,  NATANZON, Esfir ,  OSADCHIY, Ilya ,  RONEN, Ronny ,  WEISSMANN, Eliezer ,  ZACH, Yoav ,  FARRELL, Robert L.

IPC分类号： G06F12/10 ,  G06F9/06 ,  G06F9/30 ,  G06F13/14 ,  G06F12/08

CPC分类号： G06F12/1027 ,  G06F12/1036 ,  G06F12/109 ,  G06F2212/302 ,  G06F2212/682

摘要： Page faults arising in a graphics processing unit may be handled by an operating system running on the central processing unit. In some embodiments, this means that unpinned memory can be used for the graphics processing unit. Using unpinned memory in the graphics processing unit may expand the capabilities of the graphics processing unit in some cases.

公开(公告)号：EP2831693A1

公开(公告)日：2015-02-04

申请号：EP12873212.0

申请日：2012-03-30

申请人： Intel Corporation

发明人： WEISSMANN, Eliezer ,  VAITHIANATHAN, Karthikeyan Karthik ,  ZACH, Yoav ,  GINZBURG, Boris ,  RONEN, Ronny

IPC分类号： G06F1/00 ,  G06F9/06 ,  G06F12/10 ,  G06F13/14

CPC分类号： G06F12/0811 ,  G06F3/0646 ,  G06F3/0662 ,  G06F3/0668 ,  G06F9/3851 ,  G06F9/3881 ,  G06F9/3887 ,  G06F12/0292 ,  G06F12/084 ,  G06F12/0875 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1045 ,  G06F12/1072 ,  G06F12/1081 ,  G06F12/1441 ,  G06F12/145 ,  G06F2212/1024 ,  G06F2212/283 ,  G06F2212/302 ,  G06F2212/452 ,  G06F2212/60 ,  G06F2212/62 ,  G06F2212/65 ,  G06F2212/68 ,  G06F2212/683 ,  G06F2212/684

摘要： An apparatus and method are described for coupling a front end core to an accelerator component (e.g., such as a graphics accelerator). For example, an apparatus is described comprising: an accelerator comprising one or more execution units (EUs) to execute a specified set of instructions; and a front end core comprising a translation lookaside buffer (TLB) communicatively coupled to the accelerator and providing memory access services to the accelerator, the memory access services including performing TLB lookup operations to map virtual to physical addresses on behalf of the accelerator and in response to the accelerator requiring access to a system memory.

摘要翻译： 的装置和方法被描述用于耦合前端促进剂组分的芯（E. G，：诸如图形加速器）。 例如，为了装置进行说明，包括：加速器，包括一个或多个执行单元（EU）来执行指定的一组指令; 和前端芯，包括翻译旁视缓冲器（TLB）通信地耦合到所述加速器和所述加速器提供存储器访问服务，则存储器访问的服务，包括执行TLB查找操作以映射虚拟地址到物理地址代表在响应所述加速器和 在加速器需要访问系统内存。

公开(公告)号：EP3373105A1

公开(公告)日：2018-09-12

申请号：EP18169631.1

申请日：2012-03-30

申请人： Intel Corporation

发明人： WEISSMANN, Eliezer ,  VAITHIANATHAN, Karthikeyan Karthik ,  ZACH, Yoav ,  GINZBURG, Boris ,  RONEN, Ronny

IPC分类号： G06F1/00 ,  G06F9/06 ,  G06F12/10 ,  G06F13/14 ,  G06F9/38 ,  G06F12/1072 ,  G06F12/084 ,  G06F12/14 ,  G06F3/06 ,  G06F12/1027 ,  G06F12/1081 ,  G06F12/0811 ,  G06F12/1009

摘要： An apparatus and method are described for coupling a front end core to an accelerator component (e.g., such as a graphics accelerator). For example, an apparatus is described comprising: an accelerator comprising one or more execution units (EUs) to execute a specified set of instructions; and a front end core comprising a translation lookaside buffer (TLB) communicatively coupled to the accelerator and providing memory access services to the accelerator, the memory access services including performing TLB lookup operations to map virtual to physical addresses on behalf of the accelerator and in response to the accelerator requiring access to a system memory.

公开(公告)号：EP2831693B1

公开(公告)日：2018-06-13

申请号：EP12873212.0

申请日：2012-03-30

申请人： Intel Corporation

发明人： WEISSMANN, Eliezer ,  VAITHIANATHAN, Karthikeyan Karthik ,  ZACH, Yoav ,  GINZBURG, Boris ,  RONEN, Ronny

IPC分类号： G06F1/00 ,  G06F9/06 ,  G06F12/10 ,  G06F13/14 ,  G06F9/38 ,  G06F12/14 ,  G06F12/1027 ,  G06F12/1072 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/1009 ,  G06F12/1081

CPC分类号： G06F9/3851 ,  G06F3/0646 ,  G06F3/0662 ,  G06F3/0668 ,  G06F9/3881 ,  G06F9/3887 ,  G06F12/0292 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0875 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1045 ,  G06F12/1072 ,  G06F12/1081 ,  G06F12/1441 ,  G06F12/145 ,  G06F2212/1024 ,  G06F2212/283 ,  G06F2212/302 ,  G06F2212/452 ,  G06F2212/60 ,  G06F2212/62 ,  G06F2212/65 ,  G06F2212/68 ,  G06F2212/683 ,  G06F2212/684

摘要： An apparatus and method are described for coupling a front end core to an accelerator component (e.g., such as a graphics accelerator). For example, an apparatus is described comprising: an accelerator comprising one or more execution units (EUs) to execute a specified set of instructions; and a front end core comprising a translation lookaside buffer (TLB) communicatively coupled to the accelerator and providing memory access services to the accelerator, the memory access services including performing TLB lookup operations to map virtual to physical addresses on behalf of the accelerator and in response to the accelerator requiring access to a system memory.

公开(公告)号：EP2686765A1

公开(公告)日：2014-01-22

申请号：EP11861225.8

申请日：2011-12-29

申请人： Intel Corporation

发明人： GINZBURG, Boris ,  NATANZON, Esfirush ,  OSADCHIY, Ilya ,  RONEN, Ronny ,  WEISSMANN, Eliezer ,  ZACH, Yoav ,  FARRELL, Robert, L.

IPC分类号： G06F9/06 ,  G06F9/22 ,  G06F12/08 ,  G06F11/07

CPC分类号： G06F12/08 ,  G06F2212/302

摘要： Page faults arising in a graphics processing unit may be handled by an operating system running on the central processing unit. In some embodiments, this means that unpinned memory can be used for the graphics processing unit. Using unpinned memory in the graphics processing unit may expand the capabilities of the graphics processing unit in some cases.