-
公开(公告)号：EP0706115A1
公开(公告)日：1996-04-10
申请号：EP95113843.7
申请日：1995-09-04
发明人： Chappell, Barbara Alane , Chappel, Terry Ivan , Fleischer, Bruce Martin , Schuster, Stanley Everett
IPC分类号： G06F7/04 , H03K19/096
CPC分类号： G06F7/02
摘要： A fast comparator circuit, including a plurality of first switches operating in parallel. A first data bit from a first data word is input into a first input of each first switch, and a corresponding second data bit from a second data word is respectively input into a second input of each first switch. Each first switch provides a first logic state output when the first data bit matches the corresponding second data bit or a second logic state output when the first data bit does not match the second data bit. A plurality of second switches receive the respective logic state outputs and produce a combined output, indicating an all match or a mismatch, to a third switch combination connected to a first branch node and a second branch node to create a first voltage difference between the first and second branch nodes when an all match output results and a second voltage difference between the first and second branch node when a mismatch output results. A sense amplifier operates to amplify the voltage differentials that develope due to an imbalance caused in the conductance at the two branch nodes.
-
-
3.发明公开Energy discriminator, for example a colour vidicon 失效Energie-Umwandler，beispielsweise Farb-Vidicon。
公开(公告)号：EP0134411A1
公开(公告)日：1985-03-20
申请号：EP84106063.5
申请日：1984-05-28
CPC分类号： H01L27/14647 , H01J29/45
摘要： In a vidicon, optical energy enters through a transparent receiving surface (37) into a multilayer semiconductor monocrystalline body in which it is converted into hole-electron pair carriers in different particular overlying energy responsive layers (12, 13, 14) and the electrons thereof are collected in potential wells associated with the particular layer. Each pixel is isolated from adjoining pixels by isolation regions (20, 22), and readout contacts (26, 27, 29) for the layers are separated by isolation regions (28, 30).
摘要翻译： 在摄像机中，光能通过透明的接收表面（37）进入多层半导体单晶体，在多层半导体单晶体中，其被转换成不同的特定上覆能量响应层（12,13,14）及其电子的空穴 - 电子对载流子 被收集在与特定层相关联的潜在井中。 每个像素通过隔离区域（20,22）与相邻的像素隔离，并且用于层的读出触点（26,27,29）被隔离区域（28,30）隔开。
-
公开(公告)号：EP0471932A3
公开(公告)日：1992-09-16
申请号：EP91109333.4
申请日：1991-06-07
发明人： Chappell, Barbara Alane , Chappell, Terry Ivan , Ebcioglu, Mahmut Kemal , Schuster, Stanley Everett
CPC分类号： G11C8/12 , G06F12/04 , G06F12/0855 , G11C8/16
摘要： A virtual multi-port RAM (VMPRAM) structure has automatic port sequencing and single-port array density and speed. VMPRAM employs input-triggered, self-resetting macros in a pipelined architecture to provide multiple self-timed on-chip cycles during one machine cycle. The VMPRAM incorporates an SRAM segmented into many input triggered, self-resetting, fast cycling blocks. A timing signal is derived from a selected SRAM block for releasing the next select signals and data to the SRAM blocks. The SRAM block inputs are only the data input bus and the decoded signals needed to select a wordline and a bitline pair, and the SRAM block cycle is only the time needed to provide adequate pulse width for word lines and bitlines. Each SRAM block, and all the circuit blocks in the path to access the SRAM blocks, are input-triggered and self-resetting. The multiple address (35, 37, 39) and data input latches (55, 57, 59) are multiplexed at the driver to the true and complement buses to the SRAM segments, and those buses are self-resetting. Similarly, the selected SRAM block reads data out onto a self-resetting bus (63), and address (24, 26, 28) and data inputs (44, 46, 48) are latched in blocks that are set up for the release signal by the release of the adjacent block, and these blocks are all self-resetting.
-
公开(公告)号：EP0471932A2
公开(公告)日：1992-02-26
申请号：EP91109333.4
申请日：1991-06-07
发明人： Chappell, Barbara Alane , Chappell, Terry Ivan , Ebcioglu, Mahmut Kemal , Schuster, Stanley Everett
CPC分类号： G11C8/12 , G06F12/04 , G06F12/0855 , G11C8/16
摘要： A virtual multi-port RAM (VMPRAM) structure has automatic port sequencing and single-port array density and speed. VMPRAM employs input-triggered, self-resetting macros in a pipelined architecture to provide multiple self-timed on-chip cycles during one machine cycle. The VMPRAM incorporates an SRAM segmented into many input triggered, self-resetting, fast cycling blocks. A timing signal is derived from a selected SRAM block for releasing the next select signals and data to the SRAM blocks. The SRAM block inputs are only the data input bus and the decoded signals needed to select a wordline and a bitline pair, and the SRAM block cycle is only the time needed to provide adequate pulse width for word lines and bitlines. Each SRAM block, and all the circuit blocks in the path to access the SRAM blocks, are input-triggered and self-resetting. The multiple address (35, 37, 39) and data input latches (55, 57, 59) are multiplexed at the driver to the true and complement buses to the SRAM segments, and those buses are self-resetting. Similarly, the selected SRAM block reads data out onto a self-resetting bus (63), and address (24, 26, 28) and data inputs (44, 46, 48) are latched in blocks that are set up for the release signal by the release of the adjacent block, and these blocks are all self-resetting.
摘要翻译： 虚拟多端口RAM（VMPRAM）结构具有自动端口排序和单端口阵列密度和速度。 VMPRAM采用输入触发的自复位宏，采用流水线架构，在一个机器周期内提供多个自定时片上循环。 VMPRAM集成了一个SRAM，分为多个输入触发，自复位，快速循环模块。 从选择的SRAM块导出定时信号，用于将下一个选择信号和数据释放到SRAM块。 SRAM块输入只是数据输入总线和选择字线和位线对所需的解码信号，SRAM块周期只是为字线和位线提供足够的脉冲宽度所需的时间。 每个SRAM块以及访问SRAM块的路径中的所有电路块都是输入触发和自复位。 多路地址（35,37,39）和数据输入锁存器（55,57,59）在驱动器处被复用到真实和补码总线到SRAM段，并且这些总线是自复位的。 类似地，所选择的SRAM块将数据读出到自复位总线（63）上，并且将地址（24,26,28）和数据输入（44,46,48）锁存在为释放信号设置的块中 通过相邻块的释放，这些块都是自复位的。
-
-
公开(公告)号：EP0130413A3
公开(公告)日：1988-11-17
申请号：EP84106532
申请日：1984-06-08
IPC分类号： G06F05/00
摘要： A digital shifter/rotator (1000) for shifting an input word by an amount depending on a shift control word (4000) is described. The shifter/rotator comprises an array of FET pass transistors arranged in a sequential number of stages (1200, 1400, 1600, 1700, 1800). The amount to be shifted in each stage is controlled by a corresponding shift control bit on lines 4200 of the shift control word buffered by drivers 4500, whereby the output word of the rotator is the input word shifted by an amount equal to a sum of the number of shifts effected in each of the stages as determined by the shift control word. The rotator features selectable amount of shift in one machine cycle, high performance and reduced device count. Further improved performance is obtained by utilizing decoupling devices for isolating the input points of the stages, except when providing rotation, from the long rotation cross buses and its associated large parasiticcapac- itances.
-
-
公开(公告)号：EP0191544A3
公开(公告)日：1989-08-30
申请号：EP86300122.8
申请日：1986-01-09
发明人： Chappell, Barbara Alane , Rajeevakumar, Thekkemadathil Velayudan , Schuster, Stanley Everett , Terman, Lewis Madison
IPC分类号： G11C8/00
CPC分类号： G11C8/10
摘要： A decoder/driver circuit for a semiconductor memory having A1 to AN (true) and At to AN (complement) address lines for receiving A1 to AN address bit signals thereon from internal address buffers. A Ø PC line is included for receiving a Ø PC precharge clock signal thereon and a Ø R line is provided for receiving a 0 R reset clock signal thereon. The decoder/driver circuit includes a NOR decoder means having a plurality of transistor switching devices 41...44 connected to A1 to AN-1 or A1 to AN-1 of the true and complement address lines for the AN to AN-1 address bits for producing a high or low level signal on a decoder output node 1 4 depending on the address bits state. The decoder/driver circuit further includes a selection means having a plurality of transistor devices 24, 28 connected to the output node of the decoder to produce a first selection signal when the decoder output node and the AN line is high and a second selection signal when the decoder output node and the AN line is high. A driver circuit is connected to the selection means and is responsive to the output signal of the NOR decoder circuit and the first selection signal to provide an output signal on a first memory word line WLi and is further responsive to the output signal of the NOR decoder circuit and the second selection signal to provide an output sigraal on a second memory word line WLi + 1 .
-
公开(公告)号：EP0244587A2
公开(公告)日：1987-11-11
申请号：EP87103205.8
申请日：1987-03-06
CPC分类号： H03K3/356113 , H03K3/356017
摘要： A complementary input circuit is used to transfer the state of an external input (ADR IN) to the internal signal lines (ADR, ADR) of an integrated circuit chip.
A nonlinear input circuit has an input terminal (ADR IN) for receiving the external input and provides an output to a first node (a) only when the external input exceeds a reference voltage (V R ) and a threshold voltage. It comprises further latch means having first and second output nodes (b. c) connected to the internal signal lines (ADR, ADR ) of the integrated circuit chip and having an input node common to said first node (a) for receiving the output of the nonlinear input circuit, said latch means comprising transistor devices (3, 4, 5. 6) which are partially cross-coupled.摘要翻译： 该电路用于将外部输入（ADR IN）的状态转移到集成电路芯片的内部信号线（ADR，@@@）。 非线性输入电路具有用于接收外部输入的输入端（ADR IN），并且仅当外部输入超过参考电压（VR）和阈值电压时，才向第一节点（a）提供输出。 它包括另外的锁存装置，其具有连接到集成电路芯片的内部信号线（ADR，@@））的第一和第二输出节点（b，c），并且具有与所述第一节点（a）共同的输入节点，用于接收 非线性输入电路的输出，所述锁存装置包括部分交叉耦合的晶体管器件（4,5,6,7）。
-
-
-
-
-
-
-
-
-
搜索结果
31 条记录 (耗时 0.013 秒)
