摘要:
A process is described which achieves self-aligned contacts and electrodes (42, 44, 46) having very close spacing in integrated circuit devices by use of a pattern of dielectric material (30) having a thickness in the order of a micrometer or less. A pattern of recessed oxide isolation (32) between device areas in the substrate (10) is also self-aligned by this process. The result is a substantial planar integrated circuit structure. The process is applicable to either bipolar transistor integrated circuits or MOS field effect transistor integrated circuits.
摘要:
The method supplies self-aligned metal to silicon contacts and sub-micron contact-to-contact and metal-to-metal spacing in the Integrated Injection Logic (I 2 L) or Merged Transistor Logic (MTL) technology. The insulation between the contacts and the metal is a pattern of dielectric material (24, 26, 30) having a thickness dimension in the order of a micron or less. The method involves providing a silicon body (10, 12) and then forming a first insulating layer (16) on the silicon body. This layer is removed in areas designated to contain integrated injection logic devices. A layer (20) of highly doped polycrystalline silicon is formed thereover. The conductivity of the polycrystalline silicon is opposite to that of the silicon body. Openings are made in the polycrystalline I silicon layer (20) by reactive ion etching which results in the structure having substantially horizontal and vertical surfaces. The openings are formed in areas designated to be the base of the lateral injector transistor of the integrated circuit. A second insulating layer (24, 26, 30) is then formed on both the substantially horizontal surfaces and substantially vertical surfaces. Reactive ion etching of this second insulating layer (24, 26, 30) substantially removes the horizontal layers and provides a narrow dimensioned dielectric pattern of regions on the silicon body. The base of the lateral injector transistor is formed through the openings of the polycrystalline silicon layer (20). The structure is annealed to fully form the base of the transistor and to drive into the silicon body the opposite type impurities from the polycrystalline silicon layer (20) to thereby form the base regions for the vertical transistors of the integrated injection logic circuit. Additional openings and narrow dimensioned dielectric patterns are made in the polycrystalline silicon layer where the collector of the vertical transistor is to be formed. Finally the structure is contacted and planarized.
摘要:
A process is described which achieves self-aligned contacts and electrodes (42, 44, 46) having very close spacing in integrated circuit devices by use of a pattern of dielectric material (30) having a thickness in the order of a micrometer or less. A pattern of recessed oxide isolation (32) between device areas in the substrate (10) is also self-aligned by this process. The result is a substantial planar integrated circuit structure. The process is applicable to either bipolar transistor integrated circuits or MOS field effect transistor integrated circuits.
摘要:
The method supplies self-aligned metal to silicon contacts and sub-micron contact-to-contact and metal-to-metal spacing in the Integrated Injection Logic (I 2 L) or Merged Transistor Logic (MTL) technology. The insulation between the contacts and the metal is a pattern of dielectric material (24, 26, 30) having a thickness dimension in the order of a micron or less. The method involves providing a silicon body (10, 12) and then forming a first insulating layer (16) on the silicon body. This layer is removed in areas designated to contain integrated injection logic devices. A layer (20) of highly doped polycrystalline silicon is formed thereover. The conductivity of the polycrystalline silicon is opposite to that of the silicon body. Openings are made in the polycrystalline I silicon layer (20) by reactive ion etching which results in the structure having substantially horizontal and vertical surfaces. The openings are formed in areas designated to be the base of the lateral injector transistor of the integrated circuit. A second insulating layer (24, 26, 30) is then formed on both the substantially horizontal surfaces and substantially vertical surfaces. Reactive ion etching of this second insulating layer (24, 26, 30) substantially removes the horizontal layers and provides a narrow dimensioned dielectric pattern of regions on the silicon body. The base of the lateral injector transistor is formed through the openings of the polycrystalline silicon layer (20). The structure is annealed to fully form the base of the transistor and to drive into the silicon body the opposite type impurities from the polycrystalline silicon layer (20) to thereby form the base regions for the vertical transistors of the integrated injection logic circuit. Additional openings and narrow dimensioned dielectric patterns are made in the polycrystalline silicon layer where the collector of the vertical transistor is to be formed. Finally the structure is contacted and planarized.
摘要:
method for forming field effect transistor integrated circuits having a pattern of narrow dimensioned dielectric regions and more particularly a self-aligned metal process is described which achieves self-aligned metal to silicon contacts and submicron contact-to-contact and metal-to-metal spacing for field effect transistor integrated circuits. The insulation between the contacts and the metal is a pattern of dielectric material having a thickness dimension in the order of a micron or less. The metal and dielectric structure is substantially planar. The method for forming integrated circuits with this structure involves providing a silicon body (10) and then forming a first insulating layer (14) on a major surface of the silicon body. A layer of polycrystalline silicon (16) is formed thereover. Openings are made in the polycrystalline silicon layer by reactive ion etching which results in the structure having substantially horizontal surfaces (20) and substantially vertical surfaces (21). The openings can be in either the areas designated to be the gate regions or a PN junction region of the field effect transistors in the integrated circuit. A second insulating layer (22) is then formed on both the substantially horizontal surfaces (20) and substantially vertical surfaces (21). Reactive ion etching of this second insulating layer substantially removes the horizontal layers and provides a narrow dimensioned dielectric pattern of regions (22) on the major surface of the silicon body (10). The gate dielectric is either formed hereat or PN junctions are fabricated by diffusion or ion implantation techniques. The remaining polycrystalline silicon layer (16) is then removed by etching to leave the narrow dimensioned regions (22) on the major surface of the silicon body (10). A conductive layer is blanket deposited over the narrow dimensioned regions and areas in between to make contact to source;drain PN regions and form the gate electrodes. A blanker layer of a plastic material over the conductive layer is used to planarize the surface. Reactive ion etching the plastic material and the conductive layer is continued until the tops of the narrow dimensioned regions are reached leaving the structure of patterns of metal or polycrystalline silicon filling the regions between the pattern of dielectric material having having a thickness dimension in the order of a micron or less. The gate, source and drain electrodes are thusly formed.
摘要:
method for forming field effect transistor integrated circuits having a pattern of narrow dimensioned dielectric regions and more particularly a self-aligned metal process is described which achieves self-aligned metal to silicon contacts and submicron contact-to-contact and metal-to-metal spacing for field effect transistor integrated circuits. The insulation between the contacts and the metal is a pattern of dielectric material having a thickness dimension in the order of a micron or less. The metal and dielectric structure is substantially planar. The method for forming integrated circuits with this structure involves providing a silicon body (10) and then forming a first insulating layer (14) on a major surface of the silicon body. A layer of polycrystalline silicon (16) is formed thereover. Openings are made in the polycrystalline silicon layer by reactive ion etching which results in the structure having substantially horizontal surfaces (20) and substantially vertical surfaces (21). The openings can be in either the areas designated to be the gate regions or a PN junction region of the field effect transistors in the integrated circuit. A second insulating layer (22) is then formed on both the substantially horizontal surfaces (20) and substantially vertical surfaces (21). Reactive ion etching of this second insulating layer substantially removes the horizontal layers and provides a narrow dimensioned dielectric pattern of regions (22) on the major surface of the silicon body (10). The gate dielectric is either formed hereat or PN junctions are fabricated by diffusion or ion implantation techniques. The remaining polycrystalline silicon layer (16) is then removed by etching to leave the narrow dimensioned regions (22) on the major surface of the silicon body (10). A conductive layer is blanket deposited over the narrow dimensioned regions and areas in between to make contact to source;drain PN regions and form the gate electrodes. A blanker layer of a plastic material over the conductive layer is used to planarize the surface. Reactive ion etching the plastic material and the conductive layer is continued until the tops of the narrow dimensioned regions are reached leaving the structure of patterns of metal or polycrystalline silicon filling the regions between the pattern of dielectric material having having a thickness dimension in the order of a micron or less. The gate, source and drain electrodes are thusly formed.