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    A method for producing a plurality of layers of metallurgy
    1.
    发明公开
    A method for producing a plurality of layers of metallurgy 失效
    一种生产多层金属及其结构的方法

    公开(公告)号：EP0331598A3

    公开(公告)日：1991-04-10

    申请号：EP89480001.0

    申请日：1989-01-03

    申请人： International Business Machines Corporation

    发明人： Magdo, Ingrid Emese ,  Ormond, Douglas William, Jr.

    IPC分类号： H01L21/48 ,  H01L21/768

    CPC分类号： H01L21/4846 ,  H05K3/062 ,  H05K3/108 ,  H05K3/143 ,  H05K3/4629 ,  Y10S438/951

    摘要： A method for selectively depositing a plurality of metal layers on a substrate. The method includes the steps of depositing at least one layer of blanket metal (16) on a surface (10) of a substrate, building a lift-off stencil over the blanket metal, depositing at least one layer of redundant metal (24) over the lift-off stencil, depositing a first etch-resistant barrier (26) over the redundant metal, removing the lift-off stencil and the overlying layers of redundant metal and the etch-resistant barrier, depositing a second etch-resistant barrier (28) over the blanket metal and the first etch-resistant barri­er, and then reactive ion etching (RIE) the second etch-­resistant barrier so as to expose the blanket metal (16) and at least partially remove the second etch-resistant barrier from the first etch-resistant barrier. A final step of the method includes etching the blanket metal (24). Also disclosed is a metallurgical structure for a packaging substrate. The metallurgical structure includes layers of blanket metal and redundant metal. The redun­dant metal has an electrically isolating coating on its sides but not on its top surface, thereby facilitating the electrical contact of the redundant metal with the electri­cal component.

    Process for forming self-aligned metallization patterns for semiconductor devices
    3.
    发明公开
    Process for forming self-aligned metallization patterns for semiconductor devices 失效
    制造用于半导体器件的自对准的金属图案的方法。

    公开(公告)号：EP0083089A2

    公开(公告)日：1983-07-06

    申请号：EP82111971.6

    申请日：1982-12-27

    申请人： International Business Machines Corporation

    发明人： Abbas, Shakir Ahmed ,  Magdo, Ingrid Emese

    IPC分类号： H01L21/60 ,  H01L23/48

    CPC分类号： H01L29/66272 ,  H01L21/033 ,  H01L21/76801 ,  H01L21/76832 ,  H01L23/485 ,  H01L29/66545 ,  H01L29/66575 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A process is described which achieves self-aligned contacts and electrodes (42, 44, 46) having very close spacing in integrated circuit devices by use of a pattern of dielectric material (30) having a thickness in the order of a micrometer or less. A pattern of recessed oxide isolation (32) between device areas in the substrate (10) is also self-aligned by this process. The result is a substantial planar integrated circuit structure. The process is applicable to either bipolar transistor integrated circuits or MOS field effect transistor integrated circuits.

    摘要翻译： 方法描述其实现具有厚度在微米或更小的量级自对准接触和电极（42，44，46），其具有通过使用介电材料（30）的图案的在集成电路器件非常紧密的间隔。 在基板（10）的装置区域之间凹进氧化物隔离（32）的图案是这样通过该工艺自对准。 其结果是相当平坦的集成电路结构。 该方法适用于无论是双极晶体管的集成电路或MOS场效应晶体管的集成电路。

    Method for forming an integrated injection logic circuit
    4.
    发明公开
    Method for forming an integrated injection logic circuit 失效
    Verfahren zum Herstellen einer integrierten Injektions-Logikschaltung。

    公开(公告)号：EP0044426A2

    公开(公告)日：1982-01-27

    申请号：EP81104798.4

    申请日：1981-06-23

    申请人： International Business Machines Corporation

    发明人： Abbas, Shakir Ahmed ,  Magdo, Ingrid Emese

    IPC分类号： H01L21/82 ,  H01L21/60 ,  H01L27/02

    CPC分类号： H01L21/0337 ,  H01L21/8226 ,  H01L27/0233 ,  H03K19/09 ,  Y10S148/131

    摘要： The method supplies self-aligned metal to silicon contacts and sub-micron contact-to-contact and metal-to-metal spacing in the Integrated Injection Logic (I 2 L) or Merged Transistor Logic (MTL) technology. The insulation between the contacts and the metal is a pattern of dielectric material (24, 26, 30) having a thickness dimension in the order of a micron or less.
    The method involves providing a silicon body (10, 12) and then forming a first insulating layer (16) on the silicon body. This layer is removed in areas designated to contain integrated injection logic devices. A layer (20) of highly doped polycrystalline silicon is formed thereover. The conductivity of the polycrystalline silicon is opposite to that of the silicon body. Openings are made in the polycrystalline I silicon layer (20) by reactive ion etching which results in the structure having substantially horizontal and vertical surfaces. The openings are formed in areas designated to be the base of the lateral injector transistor of the integrated circuit. A second insulating layer (24, 26, 30) is then formed on both the substantially horizontal surfaces and substantially vertical surfaces. Reactive ion etching of this second insulating layer (24, 26, 30) substantially removes the horizontal layers and provides a narrow dimensioned dielectric pattern of regions on the silicon body. The base of the lateral injector transistor is formed through the openings of the polycrystalline silicon layer (20). The structure is annealed to fully form the base of the transistor and to drive into the silicon body the opposite type impurities from the polycrystalline silicon layer (20) to thereby form the base regions for the vertical transistors of the integrated injection logic circuit. Additional openings and narrow dimensioned dielectric patterns are made in the polycrystalline silicon layer where the collector of the vertical transistor is to be formed. Finally the structure is contacted and planarized.

    摘要翻译： 该方法在集成注入逻辑（I 2 L）或合并晶体管逻辑（MTL）技术中向硅接触和亚微米接触接触和金属到金属间隔提供自对准金属。 触点和金属之间的绝缘是具有一微米或更小的厚度尺寸的介电材料（24,26,30）的图案。 该方法包括提供硅体（10,12），然后在硅体上形成第一绝缘层（16）。 在指定为包含集成注入逻辑器件的区域中移除该层。 在其上形成高掺杂多晶硅层（20）。 多晶硅的导电性与硅体的导电性相反。 通过反应离子蚀刻在多晶硅层（20）中形成开口，这导致结构具有基本水平和垂直的表面。 开口形成在指定为集成电路的侧向注入器晶体管的基部的区域中。 然后在基本上水平的表面和基本垂直的表面上形成第二绝缘层（24,26,30）。 该第二绝缘层（24,26,30）的反应离子蚀刻基本上去除了水平层并且在硅体上提供了窄尺寸的区域的介电图案。 横向注射器晶体管的基底通过多晶硅层（20）的开口形成。 该结构被退火以完全形成晶体管的基极，并且从多晶硅层（20）驱动与硅体相反的杂质，从而形成用于集成注入逻辑电路的垂直晶体管的基极区域。 在要形成垂直晶体管的集电极的多晶硅层中制造附加的开口和窄尺寸的电介质图案。 最后将结构接触并平坦化。

    Method for forming integrated circuits having a pattern of narrow dimensioned dielectric regions
    5.
    发明公开
    Method for forming integrated circuits having a pattern of narrow dimensioned dielectric regions 失效
    一种用于制造具有窄尺寸的介电区域的图案的集成电路的方法。

    公开(公告)号：EP0043942A2

    公开(公告)日：1982-01-20

    申请号：EP81104797.6

    申请日：1981-06-23

    申请人： International Business Machines Corporation

    发明人： Goth, George Richard ,  Magdo, Ingrid Emese ,  Malaviya, Shashi Dhar

    IPC分类号： H01L21/60 ,  H01L21/28 ,  H01L21/00 ,  H01L21/31

    CPC分类号： H01L21/76897 ,  H01L21/0334 ,  H01L21/0337 ,  H01L21/28 ,  H01L29/41 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

    摘要： A method for forming integrated circuits having a pattern of narrow dimensioned dielectric regions and, more particularly self-aligned metal process is described which achieves self-aligned metal to silicon contacts and sub- micron contact-to-contact and metal-to-metal spacing. The insulation between the contacts and the metal is a pattern of dielectric material having a thickness dimension in the order of a micron or less. The metal and dielectric structure is substantially planar. The method for forming integrated circuits with this structure involves providing a silicon body (50, 51) and then forming a first insulating layer (52) on a major surface of the silicon body. A layer of polycrystalline silicon (53) is formed thereover. Openings are made in the polycrystalline silicon layer by reactive ion etching which results in the structure having substantially horizontal surfaces and substantially vertical surfaces. A second insulating layer (55) is then formed on both the substantially horizontal surfaces and substantially vertical surfaces. Reactive ion etching of this second insulating layer substantially removes the horizontal layers and provides a narrow dimensioned dielectric pattern of regions (56) on the major surface of the silicon body (50). The remaining polycrystalline silicon layer (53) is then removed by etching to leave the narrow dimensioned regions (56) on the major surface of the silicon body. A conductive layer is blanket deposited over the narrow dimensioned regions and areas in between. A blanket layer of a plastic material over the conductive layer to planarize the surface is accomplished. Reactive ion etching the plastic material and the conductive layer is continued until the tops of the narrow dimensioned regions (56) are reached leaving the structure of patterns (59 to 64) of metal filling the regions between the pattern of dielectric material having a thickness dimension in the order of a micron or less.

    摘要翻译： 一种用于形成具有狭窄尺寸的电介质区域的图案的集成电路的方法，并且更具体的自对准金属过程被描述其实现自对准金属硅接触和亚微米接触到接触和金属 - 金属间距 ， 触点与金属之间的绝缘是具有一微米或更小的数量级的厚度尺寸的介电材料的图案。 所述金属或介电结构是基本平坦的。 形成具有这种结构的集成电路的方法包括提供硅体（50，51），然后形成在硅主体的主表面上的第一绝缘层（52）。 多晶硅（53）的层上形成在那里。 开口中通过反应离子蚀刻，这导致结构具有基本水平表面和基本垂直的表面上的多晶硅层制成。 然后，第二绝缘层（55）形成在两个基本水平的表面和基本垂直的表面。 该第二绝缘层的反应离子蚀刻去除基本上水平层和提供区域的上硅本体（50）的主表面的窄尺寸的介电图案（56）。 剩余的多晶硅层（53）然后，通过蚀刻到离开窄尺寸的区域（56）的所述硅体的主表面上除去。 导电层是毯desposited过其间的窄尺寸的区域和地区。 塑料材料在导电层以平坦化表面的覆盖层来完成。 继续反应离子蚀刻所述塑料材料和导电层直到窄尺寸的区域的顶部（56）在达到离开的具有厚度尺寸金属的图案（59至64）填充介电材料的图案之间的区域中的结构 在微米或更小的数量级。

    Method for forming integrated circuits having a pattern of narrow dimensioned dielectric regions and resulting structures
    9.
    发明公开
    Method for forming integrated circuits having a pattern of narrow dimensioned dielectric regions and resulting structures 失效
    用于形成具有窄尺寸介电区域和结构结构的图案的集成电路的方法

    公开(公告)号：EP0043942A3

    公开(公告)日：1985-12-04

    申请号：EP81104797

    申请日：1981-06-23

    申请人： International Business Machines Corporation

    发明人： Goth, George Richard ,  Magdo, Ingrid Emese ,  Malaviya, Shashi Dhar

    IPC分类号： H01L21/60 ,  H01L21/28 ,  H01L21/00 ,  H01L21/31

    CPC分类号： H01L21/76897 ,  H01L21/0334 ,  H01L21/0337 ,  H01L21/28 ,  H01L29/41 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

    摘要： A method for forming integrated circuits having a pattern of narrow dimensioned dielectric regions and, more particularly self-aligned metal process is described which achieves self-aligned metal to silicon contacts and sub- micron contact-to-contact and metal-to-metal spacing. The insulation between the contacts and the metal is a pattern of dielectric material having a thickness dimension in the order of a micron or less. The metal and dielectric structure is substantially planar. The method for forming integrated circuits with this structure involves providing a silicon body (50, 51) and then forming a first insulating layer (52) on a major surface of the silicon body. A layer of polycrystalline silicon (53) is formed thereover. Openings are made in the polycrystalline silicon layer by reactive ion etching which results in the structure having substantially horizontal surfaces and substantially vertical surfaces. A second insulating layer (55) is then formed on both the substantially horizontal surfaces and substantially vertical surfaces. Reactive ion etching of this second insulating layer substantially removes the horizontal layers and provides a narrow dimensioned dielectric pattern of regions (56) on the major surface of the silicon body (50). The remaining polycrystalline silicon layer (53) is then removed by etching to leave the narrow dimensioned regions (56) on the major surface of the silicon body. A conductive layer is blanket deposited over the narrow dimensioned regions and areas in between. A blanket layer of a plastic material over the conductive layer to planarize the surface is accomplished. Reactive ion etching the plastic material and the conductive layer is continued until the tops of the narrow dimensioned regions (56) are reached leaving the structure of patterns (59 to 64) of metal filling the regions between the pattern of dielectric material having a thickness dimension in the order of a micron or less.