公开(公告)号：EP2243155A1

公开(公告)日：2010-10-27

申请号：EP09705024.9

申请日：2009-01-22

申请人： International Business Machines Corporation

发明人： YANG, Chih-chao ,  EDELSTEIN, Daniel, C. ,  MCFEELY, Fenton, R.

IPC分类号： H01L21/44

CPC分类号： H01L21/76826 ,  H01L21/76849 ,  H01L21/76883 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure that includes a dielectric material (52) having a dielectric constant of about 3.0 or less is provided. This low k dielectric material has at least one conductive material (60) having an upper surface embedded therein. The dielectric material also has a surface layer that is made hydrophobic (52B) prior to the formation of the noble metal cap (62). The noble metal cap is located directly on the upper surface of the at least one conductive material. Because of the presence of the hydrophobic surface layer on the dielectric material, the noble metal cap does not substantially extend onto the hydrophobic surface layer of the dielectric material that is adjacent to the at least one conductive material and no metal residues from the noble metal cap deposition form on this hydrophobic dielectric surface.

公开(公告)号：EP2008301A2

公开(公告)日：2008-12-31

申请号：EP07760071.6

申请日：2007-04-04

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： EDELSTEIN, Daniel, C. ,  FAROOQ, Mukta, G. ,  HANNON, Robert ,  MELVILLE, Ian, D.

IPC分类号： H01L21/44 ,  H01L23/48 ,  H01L23/52

CPC分类号： H01L24/03 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/03019 ,  H01L2224/039 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05083 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/1146 ,  H01L2224/13022 ,  H01L2224/13116 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/01074 ,  H01L2924/00011 ,  H01L2924/00015 ,  H01L2924/01039 ,  H01L2224/05552

摘要： A method for far back end of line (FBEOL) semiconductor device formation includes forming a terminal copper pad (104) in an upper level of a semiconductor wafer (106), forming an insulating stack (114) over the terminal copper pad, and patterning and opening a terminal via (116) within a portion of the insulating stack so as to leave a bottom cap layer of the insulating stack protecting the terminal copper pad. An organic passivation layer (126) is formed and patterned over the top of the insulating stack, and the bottom cap layer (118) over the terminal copper pad is removed. A ball limiting metallurgy (BLM) stack (128) is deposited over the organic passivation layer and terminal copper pad, and a solder ball connection (108) is formed on a patterned portion of the BLM stack.

公开(公告)号：EP1841558A2

公开(公告)日：2007-10-10

申请号：EP05852628.6

申请日：2005-12-02

申请人： International Business Machines Corporation

发明人： ANDRICACOS, Panayotis, C. ,  CANAPERI, Donald, F. ,  COOPER, Enamuel, I. ,  COTTE, John, M. ,  DELIGIANNI, Hariklia ,  ECONOMIKOS, Laertis ,  EDELSTEIN, Daniel, C. ,  FRANZ, Silvia ,  PRANATHARTHIHARAN, Balasubramanian ,  KRISHNAN, Mahadevaiyer ,  MANSSON, Andrew, P. ,  WALTON, Erick, G. ,  WEST, Alan, C.

IPC分类号： B23H3/00

CPC分类号： C25F3/02 ,  B23H5/08 ,  C09G1/04 ,  H01L21/32125

摘要： Methods and compositions for electro-chemical-mechanical polishing (e-CMP) of silicon chip interconnect materials, such as copper, are provided. The methods include the use of compositions according to the invention in combination with pads having various configurations.