公开(公告)号：EP1570517A1

公开(公告)日：2005-09-07

申请号：EP03796085.3

申请日：2003-12-08

申请人： International Business Machines Corporation

发明人： CLEVENGER, Larry ,  DALTON, Timothy ,  HOINKIS, Mark ,  KALDOR, Steffen ,  KUMAR, Kaushik ,  LA TULIPE, Douglas, Jr. ,  SEO, Soon-Cheon ,  SIMON, Andrew ,  WANG, Yun-Yu ,  YANG, Chih-Chao ,  YANG, Haining

IPC分类号： H01L21/768

CPC分类号： H01L21/76843 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76844 ,  H01L21/76847 ,  H01L21/76865

摘要： Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor (14) is covered by a capping layer (16) and a dielectric layer (18). The dielectric layer is patterned so as to expose the capping layer. The capping layer is then sputter etched to remove the capping layer and expose the metal conductor (14). In the process of sputter etching, the capping layer is redeposited (22) onto the sidewall of the pattern. Lastly, at least one layer is deposited into the pattern and covers the redeposited capping layer.

公开(公告)号：EP1570518A2

公开(公告)日：2005-09-07

申请号：EP03799543.8

申请日：2003-12-08

申请人： International Business Machines Corporation

发明人： MALHOTRA, Sandra ,  SIMON, Andrew

IPC分类号： H01L21/768

CPC分类号： H01L21/76844 ,  H01L21/76805 ,  H01L21/76865

摘要： Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor (14) is covered by a dielectric layer (18). The dielectric layer is patterned so as to expose the metal conductor. A liner layer (24) is then deposited into the pattern. The liner layer is then argon sputter etched to remove the liner layer and expose the metal conductor (14). In the process of argon sputter etching, the liner layer is redeposited onto the sidewall of the pattern. Lastly, an additional layer (26) is deposited into the pattern and covers the redeposited liner layer.

公开(公告)号：EP4410076A1

公开(公告)日：2024-08-07

申请号：EP22793729.9

申请日：2022-09-27

申请人： International Business Machines Corporation

发明人： BREW, Kevin ,  PHILIP, Timothy ,  SIMON, Andrew ,  SHOUDY, Matthew T. ,  OK, Injo

IPC分类号： H10N70/20

CPC分类号： H10N70/231 ,  H10N70/8413 ,  H10N70/826 ,  H10N70/8828 ,  H10N70/011 ,  H10N70/063

公开(公告)号：EP4388835A1

公开(公告)日：2024-06-26

申请号：EP22768348.9

申请日：2022-08-19

申请人： International Business Machines Corporation

发明人： OK, Injo ,  SAULNIER, Nicole ,  SANKARAPANDIAN, Muthumanickam ,  SIMON, Andrew ,  MCDERMOTT, Steven ,  SARAF, Iqbal

IPC分类号： H10N70/00

CPC分类号： H10N70/801 ,  H10N70/231 ,  H10N70/8413 ,  H10N70/826 ,  H10N70/8828 ,  H10N70/063

公开(公告)号：EP1570517B1

公开(公告)日：2010-06-02

申请号：EP03796085.3

申请日：2003-12-08

申请人： International Business Machines Corporation

发明人： CLEVENGER, Larry ,  DALTON, Timothy ,  HOINKIS, Mark ,  KALDOR, Steffen ,  KUMAR, Kaushik ,  LA TULIPE, Douglas, Jr. ,  SEO, Soon-Cheon ,  SIMON, Andrew ,  WANG, Yun-Yu ,  YANG, Chih-Chao ,  YANG, Haining

IPC分类号： H01L21/768

CPC分类号： H01L21/76843 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76844 ,  H01L21/76847 ,  H01L21/76865

摘要： Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor (14) is covered by a capping layer (16) and a dielectric layer (18). The dielectric layer is patterned so as to expose the capping layer. The capping layer is then sputter etched to remove the capping layer and expose the metal conductor (14). In the process of sputter etching, the capping layer is redeposited (22) onto the sidewall of the pattern. Lastly, at least one layer is deposited into the pattern and covers the redeposited capping layer.

公开(公告)号：EP1649510A2

公开(公告)日：2006-04-26

申请号：EP04741743.1

申请日：2004-06-14

申请人： International Business Machines Corporation

发明人： GAMBINO, Jeffrey ,  COONEY, Edward, III ,  STAMPER, Anthony ,  MOTSIFF, Thomas ,  LANE, Michael ,  SIMON, Andrew

IPC分类号： H01L21/768

CPC分类号： H01L21/76811 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76813 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76865 ,  H01L21/76877 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods are disclosed for forming dual damascene back-end-of-line (BEOL) interconnect structures using materials for the vias or studs which are different from those used for the line conductors, or using materials for the via liner which are different from those used for the trench liner, or having a via liner thickness different from that of the trench liner. Preferably, a thick refractory metal is used in the vias for improved mechanical strength while using only a thin refractory metal in the trenches to provide low resistance.