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18 条记录 (耗时 0.01 秒)

    Conductivity-modulation metal oxide semiconductor field effect transistor
    2.
    发明公开
    Conductivity-modulation metal oxide semiconductor field effect transistor 失效
    电导率调制金属氧化物半导体场效应晶体管

    公开(公告)号：EP0280535A3

    公开(公告)日：1990-10-10

    申请号：EP88301592.7

    申请日：1988-02-24

    申请人： KABUSHIKI KAISHA TOSHIBA

    发明人： Nakagawa, Akio c/o Patent Division ,  Yamaguchi, Yoshihiro c/o Patent Office ,  Watanabe, Kiminori c/o Patent Office

    IPC分类号： H01L29/72 ,  H01L29/06 ,  H01L29/78

    CPC分类号： H01L29/405 ,  H01L29/0696 ,  H01L29/0834 ,  H01L29/402 ,  H01L29/7393 ,  H01L29/7395 ,  H01L29/7396 ,  H01L29/7455

    摘要： A conductivity-modulation MOSFET employs a substrate (30) of an N type conductivity as its N base. A first source layer (34) of a heavily-doped N type conductivity is formed in a P base layer (32) formed in the N base (30). A source electrode (38) electrically conducts the P base (32) and the source (34). A first gate electrode (36) insulatively covers a channel region (CH1) defined by the N⁺ source layer (34) in the P base (32). A P drain layer (44) is formed on an opposite substrate surface. An N⁺ second source layer (46) is formed in a P type drain layer (44) by diffusion to define a second channel region (CH2). A second gate electrode (40) insulatively covers the second channel region (CH2), thus providing a voltage-controlled turn-off controlling transistor. A drain electrode (48) of the MOSFET conducts the P type drain (44) and second source (46). When the turn-off controlling transistor is rendered conductive to turn off the MOSFET a "shorted anode structure" is temporarily formed wherein the N type base (30) is short-circuited to the drain electrode (48), whereby case, the flow of carriers accumulated in the N type base (30) into the drain electrode is facilitated to accelerate dispersion of carriers upon turn-off of the transistor.

    Semiconductor device and method of manufacturing the same
    4.
    发明公开
    Semiconductor device and method of manufacturing the same 失效
    半导体器件及其制造方法

    公开(公告)号：EP0328331A3

    公开(公告)日：1991-03-20

    申请号：EP89301137.9

    申请日：1989-02-06

    申请人： KABUSHIKI KAISHA TOSHIBA

    发明人： Nakagawa, Akio c/o Patent Division ,  Furukawa, Kazuyoshi c/o Patent Division ,  Ogura, Tsuneo c/o Patent Division

    IPC分类号： H01L21/76

    CPC分类号： H01L21/76264 ,  H01L21/761 ,  H01L21/76275 ,  H01L21/76286 ,  H01L21/76297 ,  H01L21/763 ,  H01L27/088 ,  H01L27/1203 ,  H01L29/7394 ,  Y10S148/012

    摘要： A semiconductor device includes a semiconductor substrate, a pair of low breakdown voltage elements formed in the substrate so as to be adjacent to each other, and a high breakdown voltage element formed to be adjacent to one of the low breakdown voltage elements. The pair of low breakdown voltage elements are isolated from each other by a pn junction and the one of the low breakdown voltage elements and the high breakdown voltage element are isolated from each other by a dielectric material. The semiconductor substrate is a composite substrate formed by directly bonding a first substrate serving as an element region to a second substrate serving as a supporting member through an insulating film.

    摘要翻译： 一种半导体器件包括半导体衬底，形成在衬底中以便彼此相邻的一对低击穿电压元件以及形成为与低击穿电压元件中的一个相邻的高击穿电压元件。 这对低击穿电压元件通过pn结彼此隔离，并且低击穿电压元件之一和高击穿电压元件通过电介质材料彼此隔离。 半导体基板是通过绝缘膜将作为元件区域的第一基板直接接合到作为支撑构件的第二基板而形成的复合基板。

    Method of manufacturing semiconductor devices using a bonding process
    5.
    发明公开
    Method of manufacturing semiconductor devices using a bonding process 失效
    弗吉尼亚州的赫尔斯泰龙冯Halbleiteranordnungen手套绑架Bondierungsverfahrens。

    公开(公告)号：EP0190935A2

    公开(公告)日：1986-08-13

    申请号：EP86300821.5

    申请日：1986-02-06

    申请人： KABUSHIKI KAISHA TOSHIBA

    发明人： Nakagawa, Akio c/o Patent Division ,  Ohashi, Hiromichi c/o Patent Division ,  Ogura, Tsuneo c/o Patent Division ,  Shimbo, Masaru c/o Patent Division

    IPC分类号： H01L21/18 ,  H01L29/10 ,  H01L29/91

    CPC分类号： H01L21/02052 ,  H01L21/187

    摘要： Disclosed is a method of manufacturing a semiconductor device, comprising the step of forming a semiconductor wafer having a first impurity-doped layer and a second impurity-doped layer having a higher impurity concentration than that of the first impurity-doped layer, comprising the steps of bringing a first semiconductor substrate (11), having a third impurity-doped layer (12) which has a higher impurity concentration than that of the first impurity-doped layer and the same conductivity type as that of the second impurity-doped layer, and whose surface is mirror-polished, into contact with a second semiconductor substrate (13) having a fourth impurity doped layer, which has a higher impurity concentration than that of the first impurity-doped layer and the same conductiviey type as that of the second impurity-doped layer, and whose surface is mirror-polished, so that the mirror-polished surfaces thereof are in contact with each other, and in a clean atmosphere so that virtually no foreign substances are present therebetween, and annealing the first and second semiconductor substrates (11,13) whose mirror-polished surfaces are in contact with each other at a temperature of not less than 200°C so as to bond them together, thereby forming the second impurity-doped layer consisting of the third and fourth impurity-doped layers.

    摘要翻译： 公开了一种制造半导体器件的方法，包括形成具有第一杂质掺杂层的半导体晶片和具有比第一杂质掺杂层的杂质浓度高的杂质浓度的第二杂质掺杂层的步骤，包括步骤 带有具有比第一杂质掺杂层的杂质浓度高的第三杂质掺杂层（12）的第一半导体衬底（11）和与第二杂质掺杂层相同的导电类型的第一半导体衬底（11） 并且其表面经镜面抛光与具有第四杂质掺杂层的第二半导体衬底（13）接触，该第四杂质掺杂层具有比第一杂质掺杂层的杂质浓度更高的杂质浓度，并且具有与第二杂质掺杂层相同的导电类型 杂质掺杂层，并且其表面被镜面抛光，使得其镜面抛光表面彼此接触，并且在清洁的气氛中使得实际上没有fo 在其间存在其中存在的物质，并且在不小于200℃的温度下对其镜面抛光表面彼此接触的第一和第二半导体衬底（11,13）进行退火，以将它们结合在一起，从而形成 第二杂质掺杂层，由第三和第四杂质掺杂层组成。

    Semiconductor device and method of manufacturing the same
    8.
    发明公开
    Semiconductor device and method of manufacturing the same 失效
    Halbleiteranordnung und Verfahren zu dessen Herstellung。

    公开(公告)号：EP0328331A2

    公开(公告)日：1989-08-16

    申请号：EP89301137.9

    申请日：1989-02-06

    申请人： KABUSHIKI KAISHA TOSHIBA

    发明人： Nakagawa, Akio c/o Patent Division ,  Furukawa, Kazuyoshi c/o Patent Division ,  Ogura, Tsuneo c/o Patent Division

    IPC分类号： H01L21/76

    CPC分类号： H01L21/76264 ,  H01L21/761 ,  H01L21/76275 ,  H01L21/76286 ,  H01L21/76297 ,  H01L21/763 ,  H01L27/088 ,  H01L27/1203 ,  H01L29/7394 ,  Y10S148/012

    摘要： A semiconductor device includes a semiconductor substrate, a pair of low breakdown voltage elements formed in the substrate so as to be adjacent to each other, and a high breakdown voltage element formed to be adjacent to one of the low breakdown voltage elements. The pair of low breakdown voltage elements are isolated from each other by a pn junction and the one of the low breakdown voltage elements and the high breakdown voltage element are isolated from each other by a dielectric material. The semiconductor substrate is a composite substrate formed by directly bonding a first substrate serving as an element region to a second substrate serving as a supporting member through an insulating film.

    摘要翻译： 半导体器件包括半导体衬底，形成在衬底中彼此相邻的一对低击穿电压元件，以及形成为与低击穿电压元件之一相邻的高击穿电压元件。 一对低击穿电压元件通过pn结彼此隔离，并且低击穿电压元件和高击穿电压元件之一通过电介质材料彼此隔离。 半导体衬底是通过绝缘膜将用作元件区域的第一衬底直接接合到用作支撑构件的第二衬底上形成的复合衬底。