摘要:
Preliminary system transmitted light beam selecting means (12) comprising a 1x2 optical spatial switch and operating system transmitted light beam branching means (11) are provided in a transmitting unit (24). Received light beam switching means (9) comprising a 2x2 optical spatial switch and comprising a 2x2 optical spatial switch and preliminary system received light beam gate means (10) comprising a 1x2 optical spatial switch are provided in a receiving unit (23). Without using any 4x4 optical spatial switch, an operating system can be switched to a preliminary system. A practical optical switch involving problems such as communication cutoff for maintenance work and low use efficiency of transmission line can be provided.
摘要:
An optical signal quality monitor for simply monitoring the quality of an optical signal with high efficiency and accuracy without inviting increase in manufacturing cost, circuit scale, and power consumption. The bit rate of a monitoring signal light beam is lower than that of a main signal light beam transmitted in an optical communication system. The reception electric bandwidth of a receiver for receiving the monitoring signal light beam is equal to or wider than that of a receiver for receiving the main signal light beam. The monitoring signal light beam includes an SOH (Section Over Head) frame. Any error in the BIP (Bit Interleaved Parity) bytes of the SOH is detected. Thus, the quality of an optical communication system, especially a light-wave network is monitored.
摘要:
To perform redundant change of a child station device (52), a parent station device (51) sends a downstream PST message to the child station device (52) and after a predetermined transmission timing time sends a PLOAM grant for granting the child station device (52) to send an upstream PST message to the child station device (52).
摘要:
A parent station device (10) creates band assignment information including identification of child station devices (20-1 to 20-n) and data types transmitted by the child station devices, and sends it to the child station devices (20-1 to 20-n). Each of the child station devices (20-1 to 20-n) checks if the band assignment information is for the data type of the child station device. If the band assignment information is for the data types of the child station device, the child station device controls the transmission of data to the parent station device (10) for each data type represented by the band assignment information.
摘要:
An encoder (4) comprises flip-flop circuits (4a, 4b) which latch two-system signals having B/2 transmission speed at a B/2 frequency and output them, an adder (4f) which adds the respective output signals of the flip-flop circuits (4a, 4b) and outputs the sum, and a delayer (4e) which delays the output signal from the flip-flop circuit (4b) by 1/B hr behind the output signal from the flip-flop circuit (4a) on the input timing of the adder (4f).
摘要:
An FEC frame forming method and an FEC multiplexing method, wherein the order of information is rearranged by a first interleave circuit (32), a first error correcting code is formed by an RS (239, 223) encoding circuit (33), the order is arranged back into the original order by a first deinterleave circuit (34), and a second error correcting code is formed by an RS (255, 239) encoding circuit (5). The second error correcting code is decoded by an RS (255, 239) decoding circuit (11) to correct errors in the information, the order of information is rearranged by a second interleave circuit (35), the first error correcting code is decoded by an RS (239, 223) decoding circuit (36) to correct the remaining errors in the information, and the order is arranged back into the original order by a second deinterleave circuit (37).
摘要:
An FEC multiplexing circuit (2) is so constituted that a first memory circuit (15) is arranged at the front stage of a first RS coding circuit (16) and a second memory circuit (17) at the front stage of a second RS coding circuit (18) to execute error correction coding by a combination of different pieces of data in two directions, and then to generate an FEC frame by multiplexing the error correction codes. An FEC multiplexing/separating circuit (6) is so constituted that a third memory circuit (42) is arranged at the rear stage of a first RS decoding circuit (41) and a fourth memory circuit (44) at the rear stage of a second RS decoding circuit (43) to execute error correction by a combination of different pieces of data in two directions, and then to regenerate the original information data by multiplexing parallel data read out of the fourth memory circuit (44).