MECHANICAL FATIGUE MONITORING FOR POWER MODULE PACKAGING

    公开(公告)号:EP4403871A1

    公开(公告)日:2024-07-24

    申请号:EP23305074.9

    申请日:2023-01-23

    发明人: PERRIN, Rémi

    摘要: Power module comprising a PCB comprising at least two outer layers (11, 12) provided with metallic tracks (13, 14, 15), comprising a core layer (16) embedding one or more power semiconductor dies (17) and comprising one or more deformation sensing elements (20, 21, 22) embedded in said PCB to sense a mechanical stress in at least one axis in a three dimension coordinate system attached to the PCB. Process for measuring stress on such a power module PCB comprising an initial measurement of a deformation D0 of the PCB in use during a calibration period (100) with said strain gauges to provide a calibration of an initial deformation range of said PCB, in use measurements (110) of deformation cycles Cy of said PCB and counting (120) of said deformation cycles, repeating (150) said in use measurements during operation of said power module.

    POWER MODULE WITH INTEGRATED POWER BOARDS AND PCB BUSBAR

    公开(公告)号:EP4290574A1

    公开(公告)日:2023-12-13

    申请号:EP22305842.1

    申请日:2022-06-09

    IPC分类号: H01L23/538

    摘要: Power module, having:
    - at least a pair of integrated power boards (1a, 1b) with at least two embedded power semiconductor dies (11a, 11b, 11'a, 11'b), a first integrated power board (1a) of said pair having in line a first positive terminal (110a), a first power semiconductor die (11a), a first middle point terminal (112a, 113a), a second power semiconductor die (12a) and a first negative terminal ( 114a) and having a first current flow direction from said first negative terminal (114a) to said first positive terminal (110a), a second integrated power board (1b) of said pair having in line a second positive terminal (111b), another first power semiconductor die (11b), a second middle point terminal (113b), another second power semiconductor die (12b) and a second negative terminal (114b) and having a second current flow direction from said second negative terminal to said second positive terminal and,
    - a PCB busbar (2), to provide a positive voltage BUS+, and a negative voltage BUS-current supply to said first and second integrated power boards, having opposite first face (2a) and second face (2b) and having power conductive tracks (211a, 211b, 212a, 212b) and connection pads (21a, 21b, 22a, 22b), on both said first face and said second face, wherein said first integrated power board (1a) is positioned on said first face (2a) of the PCB busbar and has its first positive terminal (110a), first middle point terminal (112a, 113a) and first negative terminal (114a) connected to connection pads on said first face of said PCB busbar, wherein said second integrated power board (1b) is positioned on said second face (2b) of the PCB busbar has its first positive terminal (110b, 111b), first middle point terminal (112b, 113b) and first negative terminal (114b) connected to further connection pads (21b, 22b, 23b) on said second face of said PCB busbar and wherein said first integrated power board (1a) and said second integrated power board (1b) are oriented head to tail to have the first current flow direction and the second current flow direction in opposite directions.

    THERMALLY IMPROVED PCB FOR SEMICONDUCTOR POWER DIE CONNECTED BY VIA TECHNIQUE AND ASSEMBLY USING SUCH PCB

    公开(公告)号:EP4095898A1

    公开(公告)日:2022-11-30

    申请号:EP21305679.9

    申请日:2021-05-25

    摘要: Power module comprising a power semiconductor die (2) and at least one substrate (1a, 1b) comprising an insulating layer (10a, 10b) in contact with a metallized connection surface (21a, 21b) of said die and at least one conductive path (11a, 11b) on a conductive layer on a face of the insulating layer opposite to the metallized connection surface of the die and wherein said insulating layer comprises vias (3a, 3b) filled with conductive material (7) to provide connecting pads between said metallized connection surface (21a, 21b) of said die (2) and said conductive path (11a, 11b), and wherein said vias (3a, 3b) are arranged with a decreasing density from at least one hot spot position of said metallized connection surface when the die is in operation to a peripheral area of said metallized connection surface.

    METHOD AND DEVICE FOR MEASURING THE TEMPERATURE OF THE WINDINGS OF A ROTOR OF A MOTOR

    公开(公告)号:EP3863173A1

    公开(公告)日:2021-08-11

    申请号:EP20155794.9

    申请日:2020-02-06

    IPC分类号: H02P29/60

    摘要: The present invention concerns a method and a device for measuring the temperature of the windings of a rotor of a motor, the motor being a brushless wounded rotor synchronous machine that is composed of a switching cell (20) composed of transistors that are controlled by a zero voltage or current controller (70), a resonant tank (30) that is associated with a rotary transformer (40), the secondary of the rotary transformer (40) being connected to a rectifier (50) that provides DC current to the rotor windings (60). The invention :
    - obtains the switching frequency provided by the zero voltage or current controller (70) to the switching cell,
    - determines the temperature of the windings of the motor from the obtained switching frequency.

    METHOD OF FORMING HIGH DENSITY VIAS IN A MULTILAYER SUBSTRATE

    公开(公告)号:EP3745828A1

    公开(公告)日:2020-12-02

    申请号:EP19305674.4

    申请日:2019-05-28

    摘要: The invention relates to a method for manufacturing at least one array of conductive vias (100', 200', 300', 400') in a multilayer substrate (10), said substrate extending in a horizontal plane, said method comprising the steps of:
    a) forming a first array (100) of holes (101) in the substrate,
    b) filling the holes of the first array with an electrically conductive material in order to form a first array of conductive vias (100');
    c) forming a second array (200, 300, 400) of holes (201, 301, 401) in the substrate, said second array being shifted from the first array along at least one direction in the horizontal plane in a manner that each hole (201, 301, 401) of the second array is positioned between two adjacent and aligned holes (101) of the first array (100) and;
    d) filling the holes of the second array with an electrically conductive material in order to form a second array of conductive vias (200', 300', 400');
    e) repeating the steps c) and d) until that the array of conductive vias has reached the desired density of electrically conductive material with a maximum up to an area fully covered with electrically conductive material.