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    PHASE-LOCKED LOOP
    1.
    发明公开
    PHASE-LOCKED LOOP 有权
    相位控制环路

    公开(公告)号：EP1184987A4

    公开(公告)日：2004-11-17

    申请号：EP01915659

    申请日：2001-03-21

    申请人： NIPPON TELEGRAPH & TELEPHONE ,  NTT ELECTRONICS CORP

    发明人： NOSAKA HIDEYUKI ,  FUKUYAMA HIROYUKI ,  KAMITSUNA HIDEKI ,  MURAGUCHI MASAHIRO ,  YONEYAMA MIKIO ,  SASAKI HIROAKI

    IPC分类号： H03L7/087 ,  H03L7/10

    CPC分类号： H03L7/10 ,  H03L7/087

    摘要： A phase-locked loop comprises a signal path including a phase comparator, a loop filter and a voltage-controlled oscillator that are cascaded. The phase comparator compares the phases of an input signal with the phase of the output signal from the voltage-controlled oscillator and produces the result of comparison. The loop filter produces DC voltage in response to the output signal from the phase comparator. The voltage-controlled oscillator controls output oscillation frequency according to the DC output voltage from the loop filter. Voltage tracking means combines the voltage of the signal path with a signal for making the average voltage output from the phase comparator equal to a predetermined reference voltage. The voltage tracking means serves to expand the lock range of the phase-locked loop.