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53 条记录 (耗时 0.013 秒)

    CLOCK BUFFER
    2.
    发明公开
    CLOCK BUFFER 审中-公开
    TAKTPUFFER

    公开(公告)号：EP1845618A4

    公开(公告)日：2013-04-24

    申请号：EP05709760

    申请日：2005-02-04

    申请人： FUJITSU LTD

    发明人： KIBUNE MASAYA

    IPC分类号： H03K5/01 ,  G06F1/04 ,  H03F3/45 ,  H03H11/04

    CPC分类号： H03F3/45183 ,  H03F3/45197 ,  H03F3/45475 ,  H03F2203/45138 ,  H03F2203/45458 ,  H03F2203/45461 ,  H03F2203/45466 ,  H03F2203/45506 ,  H03F2203/45652 ,  H03H11/34

    摘要： To reduce noise at frequencies below the fundamental frequency of a clock and to suppress a DC component included in the clock. A clock buffer (1) has a band-pass frequency characteristic, in which a pass band of the buffer includes a fundamental frequency (f0) of a clock (CLK1) and a gain for attenuating signals, that is, a gain of less than 0 dB is provided at frequencies below the pass band. Therefore, the clock buffer can output a clock (CLK2) reduced in noise at frequencies below the fundamental frequency (f0) of the clock (CLK1). Further, the clock buffer can output the clock (CLK2) suppressed in a DC component (offset voltage) included in the clock (CLK1).

    Analog signal transmission circuit
    5.
    发明公开
    Analog signal transmission circuit 审中-公开
    模拟信号传输电路

    公开(公告)号：EP1914883A3

    公开(公告)日：2008-10-15

    申请号：EP07117657.2

    申请日：2007-10-01

    申请人： OMRON CORPORATION

    发明人： Hashimoto, Masashi c/o Omron Corporation

    IPC分类号： H03F1/26 ,  H03F3/45

    CPC分类号： H03F1/26 ,  H03F3/45183 ,  H03F2203/45466 ,  H03F2203/45506 ,  H03F2203/45548 ,  H03F2203/45674

    摘要： An analog signal transmission circuit that can suppress contamination of random noise is to be provided. A sample hold circuit is constructed by a CMOS switch, a hold capacitor, an amplifier and a pre-charge circuit. The amplifier does not operate during a sampling period, and operates during only a hold period, so that power consumption can be reduced. During the sampling period, the potential of a channel portion beneath the gate of the first transistor connected to the first terminal of the hold capacitor is stabilized with the potential of a high-potential power supply by the pre-charge circuit.

    Variable gain amplifier circuit
    6.
    发明公开
    Variable gain amplifier circuit 有权
    Schaltung eines variablenLeistungsverstärkers

    公开(公告)号：EP1928087A1

    公开(公告)日：2008-06-04

    申请号：EP07020764.2

    申请日：2007-10-24

    申请人： Mitsumi Electric Co., Ltd.

    发明人： Dobashi, Nagayoshi Mitsumi Electric Co.,Ltd. ,  Mabuchi, Shigeki Mitsumi Electric Co.,Ltd.

    IPC分类号： H03G1/00 ,  H03F3/45 ,  H03F3/72

    CPC分类号： H03G1/0023 ,  H03F3/45085 ,  H03F3/45475 ,  H03F3/72 ,  H03F2203/45138 ,  H03F2203/45506 ,  H03F2203/45528 ,  H03F2203/45652 ,  H03F2203/7231 ,  H03G1/0088

    摘要： A variable gain amplifier circuit comprises a plurality of differential circuits (22,24,26,28), each differential circuit having two input terminals and one output terminal. One of the input terminals of each amplifier is connected to a common input terminal (21) to input a signal to each of the differential circuits. Any one of the differential circuits may be selected by a switch to operate. The variable amplifier further comprises an output circuit (30) whose input terminal is connected to the output of each of the plural differential circuits, the output terminal (50) of the output circuit is connected to a series of resistors (R11,R12,R13,R14), the last resistor being connected to a reference voltage (Vref). Each of the junctions of two resistors is connected to the other one of said input terminals of said differential circuits.

    摘要翻译： 可变增益放大器电路包括多个差分电路（22,24,26,28），每个差分电路具有两个输入端和一个输出端。 每个放大器的一个输入端子连接到公共输入端子（21），以将信号输入到每个差分电路。 可以通过开关来选择差分电路中的任何一个来操作。 可变放大器还包括输入端（30），其输入端连接到多个差分电路中的每一个的输出端，输出电路的输出端（50）连接到一系列电阻（R11，R12，R13 ，R14），最后一个电阻器连接到参考电压（Vref）。 两个电阻器的每个结点连接到所述差分电路的另一个所述输入端子。

    Circuit and semiconductor device
    7.
    发明公开
    Circuit and semiconductor device 有权
    Schaltung und Halbleiterbaustein

    公开(公告)号：EP1489739A2

    公开(公告)日：2004-12-22

    申请号：EP04251144.4

    申请日：2004-02-27

    申请人： Mitsumi Electric Co., Ltd.

    发明人： Omata, Jun-Ichi, Mitsumi Electric Co., Ltd. ,  Yamanaka, Juji, Mitsumi Electric Co., Ltd. ,  Oda, Tomomi, Mitsumi Electric Co., Ltd.

    IPC分类号： H03F3/45 ,  H03F3/72 ,  H03F3/68

    CPC分类号： H03F3/3022 ,  H03F3/45183 ,  H03F3/68 ,  H03F3/72 ,  H03F2200/03 ,  H03F2203/45366 ,  H03F2203/45504 ,  H03F2203/45506 ,  H03F2203/7212

    摘要： A circuit for a power amplifier amplifies and outputs an audio signal by amplifying an input audio signal using first and second differential circuits (M41,M42,M51,M52), and driving a push-pull output transistor (M60,M62). A signal generating part generates a disconnection timing signal for disconnecting a bias current reducing activation currents of the first and second differential circuits based on a switch control signal, and positive feedback loops of the first and second differential circuits. A switch part (62,64) is disposed in each of the positive feedback loops of the first and second differential circuits, disconnecting the positive feedback loops in response to the disconnection timing signal. A bias part (M45,M55) stops the operation of the first and second differential circuits by reducing the activation currents of the first and second differential circuits by reduction of the bias currents.

    摘要翻译： 用于功率放大器的电路通过使用第一和第二差分电路（M41，M42，M51，M52）放大输入音频信号并驱动推挽输出晶体管（M60，M62）放大并输出音频信号。 信号产生部分产生断开定时信号，用于基于开关控制信号和第一和第二差分电路的正反馈回路来断开第一和第二差分电路的激活电流的偏置电流。 开关部分（62,64）设置在第一和第二差分电路的每个正反馈回路中，以响应于断开定时信号断开正反馈回路。 偏置部分（M45，M55）通过减少偏置电流来减少第一和第二差分电路的激活电流来停止第一和第二差分电路的操作。