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1.发明授权Method of manufacturing an ultra-high-density capacity comprising pillar-shaped capacitors formed on both sides of a substrate 有权形成在基板的柱状电容器的两侧超高密度的电容器布置的制造方法
公开(公告)号：EP2255376B1
公开(公告)日：2013-09-04
申请号：EP09712370.7
申请日：2009-02-17
申请人： NXP B.V.
IPC分类号： H01L21/02 , H01L21/334 , H01L23/498 , H01L27/06 , H01L27/08 , H01L29/94 , H01L29/66 , H01L27/02 , H01L21/768
CPC分类号： H01L27/0805 , H01L23/49827 , H01L27/0207 , H01L28/92 , H01L29/66181 , H01L29/945 , H01L2924/0002 , H01L2924/00
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公开(公告)号：EP1969603B1
公开(公告)日：2010-07-21
申请号：EP06842578.4
申请日：2006-12-18
申请人： NXP B.V.
IPC分类号： G11C16/04
CPC分类号： H01L29/42392 , B82Y10/00 , G11C16/0466 , H01L21/28282 , H01L21/84 , H01L27/105 , H01L27/115 , H01L27/11568 , H01L27/11573 , H01L27/1203 , H01L29/66833 , H01L29/785 , H01L29/792 , H01L29/7923
摘要： A non- volatile memory device on a semiconductor substrate having a semiconductor surface layer (2) comprises a source region (12,S), a drain region (12,D), a channel region (CO), a memory element (ME), and a gate (G). The channel region (CO) extends in a first direction (X) between the source region (12,S) and the drain region (12,D). The gate (G) is disposed near the channel region (CO) and the memory element (ME) is disposed in between the channel region (CO) and the gate. The channel region is disposed within a beam-shaped semiconductor layer (4), with the beam-shaped semiconductor layer (4a, 4b, 4c, 4d) extending in the first direction (X) between the source (12,S) and drain (12,D) regions and having lateral surfaces (4a, 4b, 4c, 4d) extending parallel to the first direction (X). The memory element comprises a charge-trapping stack (8) which covers of the lateral surfaces at least the lower surface (4c) directed towards the semiconductor surface layer (2) and the side surfaces (4b, 4d) which are directly connecting to the lower surface (4c) so as to embed the beam-shaped semiconductor layer (4) in a U-shaped form of the charge trapping stack (8).
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公开(公告)号：EP2062291A1
公开(公告)日：2009-05-27
申请号：EP07826193.0
申请日：2007-08-29
申请人： NXP B.V.
发明人： DONKERS, Johannes, J., T., M. , NUTTINCK, Sebastien , BOCCARDI, Guillaume L., R. , NEUILLY, Francois
IPC分类号： H01L21/331 , H01L29/737 , H01L29/40
CPC分类号： H01L29/7378 , H01L29/407 , H01L29/66242
摘要： The invention provides for an alternative and less complex method of manufacturing a bipolar transistor comprising a field plate (17) in a trench (7) adjacent to a collector region (21), which field plate (17) employs a reduced surface field (Resurf) effect. The Resurf effect reshapes the electric field distribution in the collector region (21) such that for the same collector-base breakdown voltage the doping concentration of the collector region (21) can effectively be increased resulting in a reduced collector resistance and hence an increased bipolar transistor speed. The method comprises a step of forming a base window (6) in a first base layer (4) thereby exposing a top surface of the collector region (21) and a part of an isolation region (3). The trench (7) is formed by removing the exposed part of the isolation region (3), after which isolation layers (9,10) are formed on the surface of the trench (7). A second base layer (13) is formed on the isolation layer (10), thereby forming the field plate (17), on the top surface of the collector region (21), thereby forming a base region (31), and on a sidewall of the first base layer (4), thereby forming an electrical connection between the first base layer (4), the base region (31) and the field plate (17). An emitter region (41) is formed on a top part of the base region (31), thereby forming the Resurf bipolar transistor.
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公开(公告)号：EP1878046A1
公开(公告)日：2008-01-16
申请号：EP06728019.8
申请日：2006-04-24
申请人： NXP B.V.
IPC分类号： H01L21/331
CPC分类号： H01L29/66272 , H01L29/0821
摘要： A method of fabricating a bipolar transistor in a first trench (11) is disclosed wherein only one photolithographic mask is applied which forms a first trench (11) and a second trench (12). A collector region (21) is formed self-aligned in the first trench (11) and the second trench (12). A base region (31) is formed self-aligned on a portion of the collector region (21), which is in the first trench (11). An emitter region (41) is formed self-aligned on a portion of the base region (31). A contact to the collector region (21) is formed in the second trench (12) and a contact to the base region (31) is formed in the first trench (11). The fabrication of the bipolar transistor may be integrated in a standard CMOS process.
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公开(公告)号：EP2062291B1
公开(公告)日：2011-11-02
申请号：EP07826193.0
申请日：2007-08-29
申请人： NXP B.V.
发明人： DONKERS, Johannes, J., T., M. , NUTTINCK, Sebastien , BOCCARDI, Guillaume L., R. , NEUILLY, Francois
IPC分类号： H01L21/331 , H01L29/737 , H01L29/40
CPC分类号： H01L29/7378 , H01L29/407 , H01L29/66242
摘要： The invention provides for an alternative and less complex method of manufacturing a bipolar transistor comprising a field plate (17) in a trench (7) adjacent to a collector region (21), which field plate (17) employs a reduced surface field (Resurf) effect. The Resurf effect reshapes the electric field distribution in the collector region (21) such that for the same collector-base breakdown voltage the doping concentration of the collector region (21) can effectively be increased resulting in a reduced collector resistance and hence an increased bipolar transistor speed. The method comprises a step of forming a base window (6) in a first base layer (4) thereby exposing a top surface of the collector region (21) and a part of an isolation region (3). The trench (7) is formed by removing the exposed part of the isolation region (3), after which isolation layers (9,10) are formed on the surface of the trench (7). A second base layer (13) is formed on the isolation layer (10), thereby forming the field plate (17), on the top surface of the collector region (21), thereby forming a base region (31), and on a sidewall of the first base layer (4), thereby forming an electrical connection between the first base layer (4), the base region (31) and the field plate (17). An emitter region (41) is formed on a top part of the base region (31), thereby forming the Resurf bipolar transistor.
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公开(公告)号：EP1878046B1
公开(公告)日：2011-03-02
申请号：EP06728019.8
申请日：2006-04-24
申请人： NXP B.V.
IPC分类号： H01L21/331
CPC分类号： H01L29/66272 , H01L29/0821
摘要： A method of fabricating a bipolar transistor in a first trench (11) is disclosed wherein only one photolithographic mask is applied which forms a first trench (11) and a second trench (12). A collector region (21) is formed self-aligned in the first trench (11) and the second trench (12). A base region (31) is formed self-aligned on a portion of the collector region (21), which is in the first trench (11). An emitter region (41) is formed self-aligned on a portion of the base region (31). A contact to the collector region (21) is formed in the second trench (12) and a contact to the base region (31) is formed in the first trench (11). The fabrication of the bipolar transistor may be integrated in a standard CMOS process.
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公开(公告)号：EP2286449A1
公开(公告)日：2011-02-23
申请号：EP09754269.0
申请日：2009-05-21
申请人： NXP B.V.
发明人： NEUILLY, Francois , MESSAOUDI, Paul
IPC分类号： H01L21/768 , H01L23/48
CPC分类号： H01L21/76898 , H01L21/76838 , H01L23/481 , H01L25/0657 , H01L2224/05001 , H01L2224/05009 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05571 , H01L2224/05684 , H01L2224/13025 , H01L2224/131 , H01L2224/16146 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06589 , H01L2924/00014
摘要： An apparatus for restricting the thermo-mechanical stress in semiconductor wafers both during manufacture, and during the operating lifetime of the semiconductor devices and systems formed on the wafer. An electrically conductive track 8 can be formed with a stopper 16 which can be positioned at least at one end of the electrically conductive track 8. The differential expansion during heating of electrically conductive tracks 8 with respect to a semiconductor wafer 4 can be restricted by the stopper 16.
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8.发明公开ULTRA HIGH DENSITY CAPACITY COMPRISING PILLAR-SHAPED CAPACITORS FORMED ON BOTH SIDES OF A SUBSTRATE 有权形成在基板的柱状电容器的两侧超高密度的电容器布置的制造方法
公开(公告)号：EP2255376A1
公开(公告)日：2010-12-01
申请号：EP09712370.7
申请日：2009-02-17
申请人： NXP B.V.
IPC分类号： H01L21/02 , H01L23/498 , H01L27/06 , H01L21/334 , H01L27/08 , H01L29/94 , H01L21/768 , H01L27/02
CPC分类号： H01L27/0805 , H01L23/49827 , H01L27/0207 , H01L28/92 , H01L29/66181 , H01L29/945 , H01L2924/0002 , H01L2924/00
摘要： The present invention describes an ultra High-Density Capacitor design, integrated in a semiconductor substrate, preferably a Si substrate, by using both wafer sides. The capacitors are pillar-shaped and comprise electrodes (930,950) separated by a dielectric layer (940).Via connections (920) are provided in trenches that go through the whole thickness of the wafer.
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公开(公告)号：EP2067167A1
公开(公告)日：2009-06-10
申请号：EP07826387.8
申请日：2007-09-14
申请人： NXP B.V.
IPC分类号： H01L21/768 , H01L23/48
CPC分类号： H01L21/76898 , H01L23/481 , H01L2224/16225 , H01L2924/00011 , H01L2924/00014 , H01L2924/15311 , H01L2924/3011 , H01L2224/0401
摘要： The present invention provides a method for making a vertical interconnect through a substrate. The method makes use of a sacrificial buried layer 220 arranged in between the first side 202 and the second side 204 of a substrate 200. After having etched trenches 206 and 206′ from the first side, the sacrificial buried layer 220 functions as a stop layer during etching of holes 218 and 218′ from the second side, therewith protecting the trenches from damage during overetch of the holes. The etching of trenches is completely decoupled from etching of the holes providing several advantages for process choice and device manufacture. After removing part of the sacrificial buried layer to interconnect the trenches and the holes, the resulting vertical interconnect hole is filled to form a vertical interconnect.
摘要翻译： 本发明提供了一种通过衬底制造垂直互连的方法。 该方法利用布置在衬底200的第一侧202和第二侧204之间的牺牲埋层220.在具有从第一侧蚀刻的沟槽206和206'之后，牺牲埋层220用作停止层 在从第二侧蚀刻孔218和218'的过程中，由此保护沟槽免于在过孔期间损坏。 沟槽的蚀刻与孔的蚀刻完全分开，为工艺选择和器件制造提供了若干优点。 在去除牺牲埋层的一部分以互连沟槽和孔之后，填充所得到的垂直互连孔以形成垂直互连。
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公开(公告)号：EP1969603A2
公开(公告)日：2008-09-17
申请号：EP06842578.4
申请日：2006-12-18
申请人： NXP B.V.
IPC分类号： G11C16/04
CPC分类号： H01L29/42392 , B82Y10/00 , G11C16/0466 , H01L21/28282 , H01L21/84 , H01L27/105 , H01L27/115 , H01L27/11568 , H01L27/11573 , H01L27/1203 , H01L29/66833 , H01L29/785 , H01L29/792 , H01L29/7923
摘要： A non- volatile memory device on a semiconductor substrate having a semiconductor surface layer (2) comprises a source region (12,S), a drain region (12,D), a channel region (CO), a memory element (ME), and a gate (G). The channel region (CO) extends in a first direction (X) between the source region (12,S) and the drain region (12,D). The gate (G) is disposed near the channel region (CO) and the memory element (ME) is disposed in between the channel region (CO) and the gate. The channel region is disposed within a beam-shaped semiconductor layer (4), with the beam-shaped semiconductor layer (4a, 4b, 4c, 4d) extending in the first direction (X) between the source (12,S) and drain (12,D) regions and having lateral surfaces (4a, 4b, 4c, 4d) extending parallel to the first direction (X). The memory element comprises a charge-trapping stack (8) which covers of the lateral surfaces at least the lower surface (4c) directed towards the semiconductor surface layer (2) and the side surfaces (4b, 4d) which are directly connecting to the lower surface (4c) so as to embed the beam-shaped semiconductor layer (4) in a U-shaped form of the charge trapping stack (8).
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