公开(公告)号：EP3166142A1

公开(公告)日：2017-05-10

申请号：EP15193403.1

申请日：2015-11-06

申请人： NXP B.V.

发明人： Tanwongwan, Wiwat ,  Suwannakha, Piyarat ,  Suwankasab, Chanon

IPC分类号： H01L23/49 ,  H01L21/60 ,  H01L23/495

CPC分类号： H01L24/48 ,  H01L21/4825 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49541 ,  H01L24/85 ,  H01L2224/32245 ,  H01L2224/48095 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2224/85047 ,  H01L2224/85181 ,  H01L2224/85205 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/3512 ,  H01L2924/386 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/85399 ,  H01L2924/00

摘要： An integrated circuit package is provided. The integrated circuit package comprises: a die (201); a lead (202); and a bond wire (205) comprising a first end coupled to the die (201) and a second end coupled to the lead (202) via bond (206). The bond wire (205) further comprises: a first portion (251) between a first bend (252) in the bond wire (205) and the bond (206) and forming a first angle with respect to the lead (202); and a second portion (253) forming a second angle with respect to the lead (202). The first bend (252) is immediately between the first (251) and second (253) portions and is configured to reduce the angle of the bond wire (205) with respect to the lead (202) from the second angle to the first angle.

摘要翻译： 提供集成电路封装。 集成电路封装包括：管芯（201）; 引线（202）; 和键合线（205），其包括耦合到管芯（201）的第一端和通过键合（206）耦合到引线（202）的第二端。 所述接合线（205）还包括：在所述接合线（205）中的第一弯曲部（252）与所述接合部（206）之间并且相对于所述引线（202）形成第一角度的第一部分（251）; 和相对于引线（202）形成第二角度的第二部分（253）。 第一弯曲部（252）紧接在第一部分（251）和第二部分（253）之间，并且被配置为将接合线（205）相对于引线（202）的角度从第二角度减小到第一角度 。

公开(公告)号：EP4195261A1

公开(公告)日：2023-06-14

申请号：EP22207302.5

申请日：2022-11-14

申请人： NXP B.V.

发明人： Saklang, Chayathorn ,  Suwankasab, Chanon ,  Saiyajitara, Amornthep ,  Vareesantichai, Verapath

IPC分类号： H01L23/495

摘要： A semiconductor package comprises a leadframe, a component module, and a semiconductor die. The leadframe has a plurality of insertion terminals, a split die pad, and one or more leads. The component module has one or more passive components mounted on a substrate. The semiconductor die has an integrated circuit. The component module is mounted on a split die pad at a first surface of the leadframe and forms an electrical connection with the insertion terminals. Further, the semiconductor die is mounted on the split die pad at a second surface of the leadframe which is opposite to the first surface.