公开(公告)号：EP4401131A1

公开(公告)日：2024-07-17

申请号：EP23151391.2

申请日：2023-01-12

申请人： Infineon Technologies Austria AG

发明人： FUERGUT, Edward ,  OTREMBA, Ralf ,  TREU, Julian ,  GAN, Thai Kee ,  BOEHM, Marcus

IPC分类号： H01L23/495

CPC分类号： H01L23/49562 ,  H01L23/4952 ,  H01L23/49537

摘要： A semiconductor package (10; 20; 30) comprising a leadframe (11; 21) comprising a die carrier (11.1) and at least one first lead (11.2; 21.2) connected with the die carrier (11.1; 21.1), a semiconductor transistor die (12) connected with the die carrier (11.1; 21.1) and comprising a first surface and a second surface opposite to the first surface, a source pad (12.1) disposed on the first surface and a drain pad disposed on the second surface, wherein the first surface faces a bottom side of the semiconductor package (10; 20; 30) and the second surface faces a top side of the package (10; 20; 30), and a clip (13) wherein the source pad (12.1) is connected with the clip (13) by at least one electrical connector (14).

公开(公告)号：EP3385981A1

公开(公告)日：2018-10-10

申请号：EP17164854.6

申请日：2017-04-04

申请人： Nexperia B.V.

发明人： Gajda, Mark Andrzej ,  Pandey, Saurabh ,  Yandoc, Ricardo Lagmay ,  Lai, Yan

IPC分类号： H01L23/00 ,  H01L23/495

CPC分类号： H01L23/49575 ,  H01L21/4825 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49562 ,  H01L24/40 ,  H01L24/48 ,  H01L2224/40137 ,  H01L2224/48245 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/13062 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/30107

摘要： Various aspects of the disclosure are directed to circuitry coupled for controlling current flow, such as in a cascode arrangement. As may be consistent with one or more embodiments, an apparatus includes a first transistor having a gate, source, channel and drain, and a second transistor having a gate, and having a stacked source, channel and drain. A conductive clip plate electrically connects the drain of the second transistor to the source of the first transistor, and another conductor electrically connects the source of the second transistor to the gate of the first transistor. The second transistor operates with the connecting structure to provide power by controlling the first transistor in an off-state and in an on-state.

公开(公告)号：EP3340286A1

公开(公告)日：2018-06-27

申请号：EP17203245.0

申请日：2017-11-23

申请人： Renesas Electronics Corporation

发明人： MATSUBARA, Yuko

IPC分类号： H01L21/607 ,  H01L23/495

CPC分类号： H01L24/48 ,  H01L21/4825 ,  H01L21/565 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49582 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/02166 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/45664 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/48824 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/78353 ,  H01L2224/83101 ,  H01L2224/83192 ,  H01L2224/83193 ,  H01L2224/83855 ,  H01L2224/85012 ,  H01L2224/85045 ,  H01L2224/85181 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85206 ,  H01L2224/92247 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2924/00015 ,  H01L2924/20301 ,  H01L2924/20305 ,  H01L2924/00

摘要： As one embodiment, a method of manufacturing a semiconductor device, the method comprising the steps of:
(a) preparing a semiconductor chip having an insulating film, and a first main surface in which a plurality of electrodes respectively exposed in a plurality of openings formed in the insulating film are formed;
(b) preparing a base material including a second main surface over which the semiconductor chip is mounted, and a plurality of terminals;
(c) after the step (a) and the step (b), mounting the semiconductor chip over the second main surface of the base material;
(d) after the step (c), electrically connecting the plurality of electrodes and the plurality of terminals via a plurality of wires, respectively; and
(e) after the step (d), resin-sealing the semiconductor chip and the plurality of wires,
wherein in that , in the step (a),
each of the plurality of electrodes of the semiconductor chip includes a first electrode having a first bonding surface exposed in a first opening among the plurality of openings, and
in a plan view, each of the plurality of openings of the semiconductor chip has a plurality of sides including a first side extending in a first direction and a second side extending in a second direction intersecting the first direction, and
wherein in that the step (d) includes the steps of:
(ST2) bringing a ball portion of a first wire among the plurality of wires into contact with the first bonding surface of the first electrode ;
(ST3) after the step (ST2), pressing the ball portion of the first wire toward the first bonding surface with a first load;
(ST4) after the step (ST3), moving the ball portion of the first wire in a plurality of directions including two directions crossing each other in a plan view while pressing the ball portion against the first electrode with a second load smaller than the first load;
(ST5) after the step (ST4), by applying a first ultrasonic wave having a first frequency to the ball portion of the first wire while pressing the ball portion against the first electrode with a third load equal to the second load or smaller than the second load, making the ball portion reciprocate along a third direction in a plan view; and
(ST6) after the step (ST5), by applying the first ultrasonic wave having the first frequency while pressing the ball portion of the first wire against the first electrode with a fourth load larger than the third load and smaller than the first load, making the ball portion reciprocate along the third direction in a plan view, thereby bonding the ball portion and the first electrode.

公开(公告)号：EP3306658A1

公开(公告)日：2018-04-11

申请号：EP17184817.9

申请日：2017-08-03

申请人： Nexperia B.V.

发明人： Yeung, Shun Tik ,  Umali, Pompeo V. ,  Lam, Kan Wae ,  Horstink, Harrie Martinus Maria ,  Walcyzk, Sven ,  Leung, Chi Ho ,  Jans, Thierry

IPC分类号： H01L23/31

CPC分类号： H01L23/49503 ,  H01L23/293 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/4952 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/528 ,  H01L24/05 ,  H01L24/06 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/06133 ,  H01L2224/48247

摘要： A semiconductor die has internal circuitry formed on two more internal layers, and die bonding pads arranged on a top surface of the die. The bonding pads are connected to the internal circuitry for providing input and output signals to the internal circuitry. One or more connecting lines electrically connect one or more pairs of the die bonding pads, thereby defining a bonding pad layout. The die bonding pads are arranged and connected with the connecting lines such that the bonding pad layout is reversible, which allows the die to be used in different package types (e.g., TSSOP or DFN) yet maintain a standardized pin arrangement without the necessity for long or crossed bond wires.

摘要翻译： 半导体管芯具有形成在两个以上内部层上的内部电路，以及布置在管芯的顶部表面上的管芯焊盘。 键合焊盘连接到内部电路，用于向内部电路提供输入和输出信号。 一个或多个连接线电连接一对或多对管芯键合焊盘，由此限定键合焊盘布局。 管芯键合焊盘被布置并连接到连接线，使得键合焊盘布局是可逆的，这允许管芯被用于不同的封装类型（例如，TSSOP或DFN），但仍保持标准化的管脚布置而不需要很长时间 或交叉的键合线。

公开(公告)号：EP3301712A1

公开(公告)日：2018-04-04

申请号：EP17189307.6

申请日：2017-09-05

申请人： MediaTek Inc.

发明人： TSAI, Shiann-Tsong

IPC分类号： H01L23/498

CPC分类号： H01L23/145 ,  H01L23/4952 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49894 ,  H01L23/5226 ,  H01L24/17 ,  H01L2924/15311

摘要： The invention provides a semiconductor package assembly. The semiconductor package assembly includes a core substrate formed of a first material having a device-attach surface and a solder-bump-attach surface opposite to the die-attach surface. A bump pad is disposed on the bump-attach surface. A first solder mask layer formed of the first material covers the bump-attach surface of the core substrate and a portion of the bump pad. A second solder mask layer covers the device-attach surface of the core substrate, wherein the second solder mask layer is formed of a second material.

摘要翻译： 本发明提供了一种半导体封装组件。 半导体封装组件包括由具有器件连接表面和与管芯连接表面相对的焊料凸点连接表面的第一材料形成的核心基板。 凸块垫布置在凸块附接表面上。 由第一材料形成的第一焊料掩模层覆盖核心基板的凸块附接表面和凸块焊盘的一部分。 第二焊料掩模层覆盖核心基板的器件接合表面，其中第二焊料掩模层由第二材料形成。

公开(公告)号：EP3142144A4

公开(公告)日：2018-03-21

申请号：EP14891180

申请日：2014-05-09

申请人： MITSUBISHI ELECTRIC CORP

发明人： FUSHIE SHUNSUKE ,  KAWANO YU ,  ASAO YOSHIHITO

IPC分类号： H01L21/60 ,  H01L23/495 ,  H01L25/07 ,  H02M7/00

CPC分类号： H01L23/49562 ,  H01L21/4825 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/495 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49575 ,  H01L24/29 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/84 ,  H01L2224/0603 ,  H01L2224/26175 ,  H01L2224/291 ,  H01L2224/32245 ,  H01L2224/37147 ,  H01L2224/3716 ,  H01L2224/40139 ,  H01L2224/40245 ,  H01L2224/40499 ,  H01L2224/48247 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/83385 ,  H01L2224/83815 ,  H01L2224/84385 ,  H01L2224/84815 ,  H01L2924/00014 ,  H01L2924/13055 ,  H01L2924/13091 ,  H02M7/003 ,  H02M7/537 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2224/45099

摘要： A semiconductor module can be realized, which is formed by mounting an electronic component and a bus bar by solder on a lead frame including a plurality of terminals, wherein a solder flow suppressing section capable of restricting a direction of flow of solder on the lead frame is formed in the vicinity of the solder portion of the component mounted by solder, and by this configuration, positional deviation, such as rotation or movement of the mounted component, is suppressed and the size of the module can be made compact.

公开(公告)号：EP3093886B1

公开(公告)日：2018-03-21

申请号：EP16166286.1

申请日：2016-04-20

申请人： Honeywell International Inc.

发明人： KATTI, Romney R. ,  TUCKER, James L.

IPC分类号： H01L25/065 ,  H01L23/552 ,  H01L21/98 ,  H01L21/60

CPC分类号： H01L23/49575 ,  H01L21/4825 ,  H01L21/4871 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49568 ,  H01L23/552 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/80 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04 ,  H01L2224/04042 ,  H01L2224/05647 ,  H01L2224/06135 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48464 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48472 ,  H01L2224/49109 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/80203 ,  H01L2224/80447 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/8148 ,  H01L2224/81484 ,  H01L2224/81801 ,  H01L2224/83801 ,  H01L2224/85424 ,  H01L2224/85439 ,  H01L2224/85447 ,  H01L2224/8548 ,  H01L2224/85484 ,  H01L2224/92165 ,  H01L2224/9222 ,  H01L2224/92247 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06537 ,  H01L2225/06562 ,  H01L2225/06575 ,  H01L2225/06589 ,  H01L2225/06593 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/1435 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2224/32145 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2224/80 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2224/32245 ,  H01L2224/48247

摘要： A stacked integrated circuit (IC) system including a substrate, a contour support, and a first and second IC dies. The contour support including a first support frame attached to the substrate defining a first lateral contact surface substantially orthogonal to the substrate, a support plate on the first support frame substantially parallel to the substrate, and a second support frame on the support plate defining a second lateral contact surface substantially orthogonal to the substrate, with the first and second lateral contact surfaces laterally offset from each other. The first integrated circuit die with a side abutting the first lateral contact surface, the second integrated circuit die with a side abutting the second lateral contact surface such that at least a portion of the support plate is between the first and second integrated circuit dies.

公开(公告)号：EP2362417B1

公开(公告)日：2018-01-10

申请号：EP11004204.1

申请日：2009-09-02

申请人： Linear Technology Corporation

发明人： Pruitt, David, A.

IPC分类号： H01L23/64 ,  H01L23/495 ,  H01F19/08

CPC分类号： H01F19/08 ,  H01F38/14 ,  H01F2019/085 ,  H01F2027/2814 ,  H01L23/48 ,  H01L23/4952 ,  H01L23/642 ,  H01L23/645 ,  H01L24/05 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0655 ,  H01L25/072 ,  H01L2223/6611 ,  H01L2224/04042 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48195 ,  H01L2224/4823 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/48491 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2224/48755 ,  H01L2224/48847 ,  H01L2224/48855 ,  H01L2224/49052 ,  H01L2224/4912 ,  H01L2224/49175 ,  H01L2224/49176 ,  H01L2224/4943 ,  H01L2224/85455 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2224/48824

摘要： A semiconductor device is configured to provide current and voltage isolation inside an integrated circuit package. The semiconductor device includes first and second semiconductor dies, a first isolating block positioned on the first semiconductor die, and a second isolating block positioned on the second semiconductor die. The semiconductor device also includes a first interconnect coil having a plurality of wires connecting the first semiconductor die to the second isolating block, and a second interconnect coil having a plurality of wires connecting the second semiconductor die to the first isolating block.

公开(公告)号：EP3216058A1

公开(公告)日：2017-09-13

申请号：EP15856210.8

申请日：2015-11-04

申请人： Texas Instruments Incorporated

发明人： EUGENE LEE, Lee Han Meng ,  BIN ABDUL AZIZ, Anis Fauzi ,  FEN, Sueann Lim Wei

IPC分类号： H01L27/085

CPC分类号： H01L25/50 ,  H01L21/4825 ,  H01L21/4853 ,  H01L21/561 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/4952 ,  H01L23/49534 ,  H01L23/49537 ,  H01L23/49551 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49844 ,  H01L24/34 ,  H01L24/37 ,  H01L24/38 ,  H01L24/48 ,  H01L24/85 ,  H01L24/97 ,  H01L25/071 ,  H01L25/165 ,  H01L25/18 ,  H01L2224/291 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/371 ,  H01L2224/37147 ,  H01L2224/37599 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2224/92246 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/1301 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05599

摘要： A method for forming a stacked semiconductor package includes providing a bottom leadframe (LF) panel including LFs downset each including at least a plurality of terminals. Low side (LS) transistors are attached to the first die attach area. A first clip panel including first clips downset and interconnected are placed on the bottom LF panel. A dielectric interposer is attached on the first clips over the LS transistors. High side (HS) transistors are attached on the interposers. A second clip panel including a plurality of second clips is mated to interconnect to the HS transistors including mating together the second clip panel, first clip panel and bottom LF panel. The LFs can include a second die attach area, and a controller die attached on the second die attach area, and then pads of the controller die wirebonded to the plurality of terminals.

摘要翻译： 一种用于形成堆叠式半导体封装的方法包括提供包括倒置的LF的底部引线框架（LF）面板，每个LF包括至少多个端子。 低侧（LS）晶体管连接到第一管芯附着区域。 包括倒置并互连的第一夹子的第一夹子面板放置在底部LF面板上。 介质插入器连接在LS晶体管上的第一个夹子上。 高端（HS）晶体管连接在插入器上。 包括多个第二夹子的第二夹子面板配合以互连至HS晶体管，包括将第二夹子面板，第一夹子面板和底部LF面板配合在一起。 LF可以包括第二管芯附着区域和附着在第二管芯附着区域上的控制器管芯，然后将控制器管芯的焊盘引线键合到多个端子。

公开(公告)号：EP3058663A4

公开(公告)日：2017-09-13

申请号：EP14854470

申请日：2014-10-20

申请人： KEYSSA INC

发明人： MCCORMACK GARY D ,  SOVERO EMILIO ,  SWEETMAN ERIC ,  ZIVANOVIC BOJANA

IPC分类号： H04B5/00

CPC分类号： H04B1/123 ,  H01L23/3107 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/66 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L2223/6677 ,  H01L2224/131 ,  H01L2224/16245 ,  H01L2224/32227 ,  H01L2224/48227 ,  H01L2224/48245 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H04B5/0031 ,  H04B5/02 ,  Y02D70/00 ,  Y02D70/12 ,  Y02D70/122 ,  Y02D70/166 ,  Y02D70/42 ,  H01L2224/45099 ,  H01L2924/014 ,  H01L2924/00012

摘要： Contactless extremely high frequency (EHF) signal directing and blocking structures are disclosed herein. The EHF signal directing structures may focus EHF signal energy along a desired EHF signal pathway. The EHF signal blocking structures may minimize signal propagation through substrates such as circuit boards. Focusing EHF signal energy and selectively blocking the EHF signal energy can minimize or eliminate crosstalk and enhance data transmission speed and integrity.

摘要翻译： 本文公开了非接触式极高频率（EHF）信号引导和阻挡结构。 EHF信号引导结构可以将EHF信号能量集中在期望的EHF信号路径上。 EHF信号阻挡结构可以使通过诸如电路板等基板的信号传播最小化。 聚焦EHF信号能量并有选择地阻止EHF信号能量可以最小化或消除串扰并提高数据传输速度和完整性。