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公开(公告)号：EP1119922B1
公开(公告)日：2007-01-03
申请号：EP99954885.2
申请日：1999-10-12
发明人： BUTLER, Brian, K. , ZHANG, Haitao , TIEDEMANN, Edward, G., Jr. , ZOU, Qiuzhen , SIH, Gilbert, C. , AGRAWAL, Avneesh
CPC分类号： H04B1/70751 , H04B1/7077 , H04B1/70775 , H04B1/7115 , H04B2201/70701 , H04B2201/70702 , H04W52/0229 , Y02D70/40
摘要： A novel and improved method for performing paging is described. In one embodiment of the invention a searcher is used to detect spread spectrum signals. Samples received RF signals are stored in a sample buffer. During standby mode, the samples are gathered during paging slots assigned to the mobile. A set of searches are performed on the samples, and if pilot signals are detected additional demodulation is performed to detect paging messages. The resulting set of demodulation data may be combined to increase detection. After a page message has been detected, additional demodulation resources may be activated to processes more complete page messages, or other information channels. In one embodiment of the invention, the searcher includes a demodulator to perform quick page detection without the use of finger elements to reduce idle mode power consumption.
摘要翻译： 描述了用于执行寻呼的新颖且改进的方法。 在本发明的一个实施例中，搜索器用于检测扩频信号。 将接收到的射频信号样本存储在样本缓冲区中。 在待机模式下，样本在分配给移动台的寻呼时隙期间收集。 对样本执行一组搜索，并且如果检测到导频信号，则执行额外的解调以检测寻呼消息。 所得到的一组解调数据可以被组合以增加检测。 在检测到寻呼消息之后，可以激活附加的解调资源以处理更完整的寻呼消息或其他信息信道。 在本发明的一个实施例中，搜索器包括解调器，以执行快速页面检测而不使用手指元素来减少空闲模式功耗。
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2.发明公开METHOD AND APPARATUS FOR CANCELING PILOT INTERFERENCE IN A CDMA COMMUNICATION SYSTEM 审中-公开用于消除CDMA通信系统中的导频干扰的方法和设备
公开(公告)号：EP1327311A2
公开(公告)日：2003-07-16
申请号：EP01987972.5
申请日：2001-10-16
IPC分类号： H04B1/707
CPC分类号： H04B1/7107
摘要： Techniques for canceling pilot interference in a wireless (e.g., CDMA) communication system. A received signal typically includes a number of signal instances (i.e., multipaths). For each multipath desired to be processed, the other multipaths act as interference on the desired multipath. If the pilot is generated based on a known data pattern (e.g., all zeros) and covered with a known channelization code (e.g., a Walsh code of zero), then the pilot in an interfering multipath may be estimated as the spreading sequence at a time offset corresponding to the arrival time of that multipath. The pilot interference from each interference multipath may be estimated based on the spreading sequence for the interfering multipath and the despreading sequence for the desired multipath. The total pilot interference from a number of interfering multipaths may be subtracted from the data component in the desired multipath to provide pilot-canceled data having improved performance.
摘要翻译： 用于消除无线（例如，CDMA）通信系统中的导频干扰的技术。 接收的信号通常包括多个信号实例（即，多路径）。 对于需要处理的每个多路径，其他多路径对期望的多路径起干扰作用。 如果基于已知数据模式（例如，全零）生成导频并且用已知信道化码（例如，零的沃尔什码）覆盖导频，则可以将干扰多径中的导频估计为 时间偏移对应于该多路径的到达时间。 可以基于干扰多径的扩频序列和期望多径的解扩序列来估计来自每个干扰多径的导频干扰。 可以从所需多径中的数据分量中减去来自多个干扰多径的总导频干扰，以提供具有改进性能的导频消除数据。
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3.发明公开A METHOD OF AND APPARATUS FOR PAGING A WIRELESS TERMINAL IN A WIRELESS TELECOMMUNICATIONS SYSTEM 失效方法和装置，用于间接寻呼的无线终端以较少的编码的寻呼解释。
公开(公告)号：EP0985325A2
公开(公告)日：2000-03-15
申请号：EP98924967.7
申请日：1998-05-29
IPC分类号： H04Q7/38
CPC分类号： H04W68/00 , H04L1/0017 , H04L1/0025 , H04W48/12 , H04W52/0216 , H04W52/0219 , H04W68/02 , H04W68/025 , H04W68/08 , H04W84/042 , Y02D70/00
摘要： The method pages (fig 2) a wireless terminal in a wireless telecommunications system and transmits a quick page message via a less encoded channel and generates a full page message via a more encoded channel. The quick page massege contains less information than the full page message. The quick page message is for notifying the wireless terminal to begin processing for the full page message, and comprises a single bit of data. The full page message is transmitted during a second time slot assigned to the wireless terminal that occurs after the first time slot.
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公开(公告)号：EP0812491A1
公开(公告)日：1997-12-17
申请号：EP96945650.0
申请日：1996-12-23
发明人： BUTLER, Brian, K.
CPC分类号： H03G3/3042 , H03F1/3241
摘要： A system for substantially eliminating nonlinear distortion, such as intermodulation products, introduced when a signal is processed by a nonlinear device (106). The system adds an out-of-band signal (111) to an input signal (101) to produce a combined signal (105) having a power that substantially equals a nominal operating point power for a nonlinear device (106). Preferably, the instantaneous power of the out-of-band signal (111) is adjusted by an automatic gain amplifier (120). The combined signal (105) is input to the nonlinear device (106) to produce an output. A filter (108) processes the output of the nonlinear device (106) to recover the information content of the original signal (101) after processing by the nonlinear device (106). For example, if the nonlinear device (106) is a power amplifier, the filtered output (109) is an amplification of the input signal (101).
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5.发明公开MULTIRATE SERIAL VITERBI DECODER FOR CODE DIVISION MULTIPLE ACCESS SYSTEM APPLICATIONS 失效串行维特比解码器，用于不同的比特CDMA系统
公开(公告)号：EP0720797A1
公开(公告)日：1996-07-10
申请号：EP94929870.0
申请日：1994-09-23
CPC分类号： H03M13/3776 , H03M13/37 , H03M13/41 , H04B1/707 , H04B2201/70703 , H04L1/0009 , H04L1/0032 , H04L1/0046 , H04L1/0052 , H04L1/0054 , H04L1/0071 , H04L1/08 , H04L1/20 , H04L1/208 , H04L25/0262 , H04L25/03178
摘要： A Viterbi decoder (20) for recovering the original bit data stream that was convolutionally encoded as a code symbol stream in a Code Division Multiple Access (CDMA) mobile communication system (22). The decoder (20) simultaneously decodes at the several data rates associated with certain multirate vocoders. The decoder (20) can decode at an unknown data rate in either continuous or framed packed modes. It accomplishes this by simultaneously decoding at multiple rates and by creating one or more data quality metrics for each decoded data packet. Special input and output buffering is provided to isolate the decoder (50) from system timing constraints. The input buffer (48) includes selection and accumulation logic to organize code symbol data into the packet order for repeat mode or random burst mode at lower frame data rates. Decoded data packets for each of several predetermined data transfer rates are held in an output buffer (54) for about half of the decoding cycle, thereby permitting the system microprocessor to examine and select the appropriate decoded data packet. The decoder (50) also can be reconfigured to operate at any one of several predetermined convolutional encoding algorithms. The Viterbi decoder (20), implemented as a single monolithic integrated circuit, can be used in any and all of many different multiuser telecommunications channels.
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公开(公告)号：EP1464121A2
公开(公告)日：2004-10-06
申请号：EP02794135.0
申请日：2002-12-03
发明人： BUTLER, Brian, K. , WOLF, Jack, K. , MILNE, Ryan
CPC分类号： H03M13/6502 , H03M13/1515 , H03M13/19 , H03M13/2909 , H03M13/293 , H03M13/37
摘要： Techniques for low computation (1) erasure-and-single-error correction block decoding on a received block of symbols previously coded column-wise with an (N, K) linear error correction block code (e.g. a Reed-Solomon code) and row-wise with an error detection code (e.g., a CRC code). Initially, each row of the received block is marked as either an erased row or an un-erased row based on error detection decoding. To perform erasure-and-single-error correction block decoding on the received block, a codeword corresponding to a column of the received block containing an undetected symbol error is initially identified using the error correction code. The location of the symbol error in the codeword is then determined based on a particular block decoding scheme and corresponding to the selected (N, K) block code. The row of the received block containing the symbol error is then marked as an erased row. Block decoding may then be performed for the received block with the newly marked erased row containing the symbol error.
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7.发明公开METHOD AND SYSTEM FOR UTILIZATION OF AN OUTER DECODER IN A BROADCAST SERVICES COMMUNICATION SYSTEM 有权方法和系统对于使用外部解码器在广播服务通信系统
公开(公告)号：EP1421719A2
公开(公告)日：2004-05-26
申请号：EP02757147.0
申请日：2002-08-15
发明人： CHEN, Tao , WOLF, Jack, K. , ODENWALDER, Joseph, P. , TIEDEMANN, Edward, G., Jr. , BUTLER, Brian, K. , WEI, Yongbin
IPC分类号： H04H1/00
CPC分类号： H03M13/3715 , H03M13/09 , H03M13/2909 , H03M13/293 , H04H20/30 , H04W52/0219 , H04W52/0245 , H04W52/322 , H04W72/005 , Y02D70/1222 , Y02D70/1242
摘要： A Method and System for Utilization of an Outer Decoder in a Broadcast Services Communication System is described. An outer decoder and an inner decoder encode a block of information to be transmitted, to improve protection by adding redundancy. The redundancy permits decoding of the information from less than a complete encoded block of information. Consequently, the receiving station determines when sufficient amount of information for successful decoding has been received, and utilizes the time remaining before the next block of information arrives to perform other activities, e.g., hard handoff on a broadcast channel, inter-frequency hard handoff, and other activities. Alternatively, the receiving station can cease reception, thus decrease power consumption. Furthermore, part of the information block may be utilized for transmission of signaling information.
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公开(公告)号：EP1332552A2
公开(公告)日：2003-08-06
申请号：EP01992057.8
申请日：2001-11-03
IPC分类号： H03H1/00
CPC分类号： H03H17/0657 , H03H17/0226 , H03H17/0238 , H03H17/06 , H03H17/0607
摘要： A system for digital filtering includes a set of logic gates, a state storage, and a multiplexer. The state storage includes two or more storage banks and may also include combinatorial logic and/or at least one lookup table. In one application, a filtering operation according to a finite-impulse-response filter coefficient vector is performed without runtime multiplications. Applications to symmetric and antisymmetric filter coefficient vectors are described, as well as applications to filter coefficient vectors of arbitrary odd or even length.
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9.发明授权MULTIRATE SERIAL VITERBI DECODER FOR CODE DIVISION MULTIPLE ACCESS SYSTEM APPLICATIONS 失效串行维特比解码器，用于不同的比特CDMA系统
公开(公告)号：EP0720797B1
公开(公告)日：2001-12-05
申请号：EP94929870.7
申请日：1994-09-23
CPC分类号： H03M13/3776 , H03M13/37 , H03M13/41 , H04B1/707 , H04B2201/70703 , H04L1/0009 , H04L1/0032 , H04L1/0046 , H04L1/0052 , H04L1/0054 , H04L1/0071 , H04L1/08 , H04L1/20 , H04L1/208 , H04L25/0262 , H04L25/03178
摘要： A Viterbi decoder (20) for recovering the original bit data stream that was convolutionally encoded as a code symbol stream in a Code Division Multiple Access (CDMA) mobile communication system (22). The decoder (20) simultaneously decodes at the several data rates associated with certain multirate vocoders. The decoder (20) can decode at an unknown data rate in either continuous or framed packed modes. It accomplishes this by simultaneously decoding at multiple rates and by creating one or more data quality metrics for each decoded data packet. Special input and output buffering is provided to isolate the decoder (50) from system timing constraints. The input buffer (48) includes selection and accumulation logic to organize code symbol data into the packet order for repeat mode or random burst mode at lower frame data rates. Decoded data packets for each of several predetermined data transfer rates are held in an output buffer (54) for about half of the decoding cycle, thereby permitting the system microprocessor to examine and select the appropriate decoded data packet. The decoder (50) also can be reconfigured to operate at any one of several predetermined convolutional encoding algorithms. The Viterbi decoder (20), implemented as a single monolithic integrated circuit, can be used in any and all of many different multiuser telecommunications channels.
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10.发明公开
公开(公告)号：EP1106027A1
公开(公告)日：2001-06-13
申请号：EP99942205.8
申请日：1999-08-13
CPC分类号： G06F1/08 , G06F1/3203 , G06F1/324 , H03L7/00 , H04B1/1615 , H04L7/033 , H04W52/0216 , Y02D10/126 , Y02D70/1222 , Y02D70/40
摘要： A method and circuit for controlling a mobile station operating in a slotted paging environment. The circuit comprises a low power clock for generating a low frequency clock signal; a clock signal generator for generating a high frequency clock signal; a synchronization logic circuit for synchronizing the low frequency clock signal to the high frequency clock signal; a frequency error estimator for measuring an estimated low frequency clock error; and a sleep controller for removing power from the clock signal generator for the corrected sleep duration value, thereby conserving power between assigned paging slots. During the awake time, the low frequency clock signal is resynchronized to the high frequency clock, thereby correcting for any frequency error in the less accurate low power clock during sleep mode.
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