公开(公告)号：EP1974255B1

公开(公告)日：2018-08-22

申请号：EP07710244.0

申请日：2007-01-22

申请人： QUALCOMM Incorporated

发明人： KOPEC, Brian Joseph ,  AUGSBURG, Victor Roberts ,  DIEFFENDERFER, James Norris ,  BRIDGES, Jeffrey Todd ,  SARTORIUS, Thomas Andrew

IPC分类号： G06F9/38

CPC分类号： G06F9/3861 ,  G06F12/1027

摘要： A processor having a multistage pipeline includes a TLB and a TLB controller. In response to a TLB miss signal, the TLB controller initiates a TLB reload, requesting address translation information from either a memory or a higher-level TLB, and placing that information into the TLB. The processor flushes the instruction having the missing virtual address, and refetches the instruction, resulting in re-insertion of the instruction at an initial stage of the pipeline above the TLB access point. The initiation of the TLB reload, and the flush/refetch of the instruction, are performed substantially in parallel, and without immediately stalling the pipeline. The refetched instruction is held at a point in the pipeline above the TLB access point until the TLB reload is complete, so that the refetched instruction generates a “hit” in the TLB upon its next access.

公开(公告)号：EP1866773A2

公开(公告)日：2007-12-19

申请号：EP06739038.5

申请日：2006-03-17

申请人： QUALCOMM INCORPORATED

发明人： SARTORIUS, Thomas Andrew ,  BRIDGES, Jeffrey Todd ,  DIEFFENDERFER, James Norris ,  AUGSBURG, Victor Roberts

IPC分类号： G06F12/10

CPC分类号： G06F12/1027 ,  G06F2212/652

摘要： A system for optimizing translation lookaside buffer entries is provided. The system includes a translation lookaside buffer configured to store a number of entries, each entry having a size attribute, each entry referencing a corresponding page, and control logic configured to modify the size attribute of an existing entry in the translation lookaside buffer if a new page is contiguous with an existing page referenced by the existing entry. The existing entry after having had its size attribute modified references a consolidated page comprising the existing page and the new page.

公开(公告)号：EP1979819B1

公开(公告)日：2019-12-18

申请号：EP07762667.9

申请日：2007-01-31

申请人： QUALCOMM Incorporated

发明人： AUGSBURG, Victor Roberts ,  DIEFFENDERFER, James Norris ,  BRIDGES, Jeffrey Todd ,  SARTORIUS, Thomas Andrew

IPC分类号： G06F12/0888 ,  G06F9/30 ,  G06F9/38

公开(公告)号：EP1934753B1

公开(公告)日：2018-08-08

申请号：EP06789946.8

申请日：2006-08-22

申请人： QUALCOMM Incorporated

发明人： AUGSBURG, Victor Roberts ,  DIEFFENDERFER, James Norris ,  BRIDGES, Jeffrey Todd ,  SARTORIUS, Thomas Andrew

IPC分类号： G06F12/1027 ,  G06F12/126 ,  G06F12/12 ,  G06F12/10

CPC分类号： G06F12/1027 ,  G06F12/126 ,  G06F2212/681

摘要： A processor includes a hierarchical Translation Lookaside Buffer (TLB) comprising a Level-1 TLB and a small, high-speed Level-0 TLB. Entries in the L0 TLB replicate entries in the L1 TLB. The processor first accesses the L0 TLB in an address translation, and access the L1 TLB if a virtual address misses in the L0 TLB. When the virtual address hits in the L1 TLB, the virtual address, physical address, and page attributes are written to the L0 TLB, replacing an existing entry if the L0 TLB is full. The entry may be locked against replacement in the L0 TLB in response to an L0 Lock (L0L) indicator in the L1 TLB entry. Similarly, in a hardware-managed L1 TLB, entries may be locked against replacement in response to an L1 Lock (L1L) indicator in the corresponding page table entry.

公开(公告)号：EP1849061A2

公开(公告)日：2007-10-31

申请号：EP06735444.9

申请日：2006-02-16

申请人： QUALCOMM INCORPORATED

发明人： BRIDGES, Jeffrey Todd ,  AUGSBURG, Victor Roberts ,  DIEFFENDERFER, James Norris ,  SARTORIUS, Thomas Andrew

IPC分类号： G06F9/312 ,  G06F9/38 ,  G06F9/318

CPC分类号： G06F9/30043 ,  G06F9/30145 ,  G06F9/30189 ,  G06F9/3824 ,  G06F9/3832 ,  G06F9/3855

摘要： In an instruction execution pipeline, the misalignment of memory access instructions is predicted. Based on the prediction, an additional micro-operation is generated in the pipeline prior to the effective address generation of the memory access instruction. The additional micro-operation accesses the memory falling across a predetermined address boundary. Predicting the misalignment and generating a micro-operation early in the pipeline ensures that sufficient pipeline control resources are available to generate and track the additional micro-operation, avoiding a pipeline flush if the resources are not available at the time of effective address generation. The misalignment prediction may employ known conditional branch prediction techniques, such as a flag, a bimodal counter, a local predictor, a global predictor, and combined predictors. A misalignment predictor may be enabled or biased by a memory access instruction flag or misaligned instruction type.

摘要翻译： 在指令执行流水线中，预测存储器访问指令的未对准。 基于该预测，在存储器访问指令的有效地址生成之前在流水线中生成附加的微操作。 附加的微操作访问落在预定地址边界的存储器。 预测未对准并在管道早期生成微操作确保足够的流水线控制资源可用于生成和跟踪附加的微操作，如果资源在有效地址生成时不可用，则避免管道冲洗。 未对准预测可以使用已知的条件分支预测技术，例如标志，双模计数器，局部预测器，全局预测器和组合预测器。 未对准预测器可能被存储器访问指令标志或未对准指令类型启用或偏置。

公开(公告)号：EP1934754B1

公开(公告)日：2018-12-26

申请号：EP06815156.2

申请日：2006-09-21

申请人： Qualcomm Incorporated

发明人： STEMPEL, Brian Michael ,  DIEFFENDERFER, James Norris ,  BRIDGES, Jeffrey Todd ,  SARTORIUS, Thomas Andrew ,  SMITH, Rodney Wayne ,  CLANCY, Robert Douglas ,  AUGSBURG, Victor Roberts

IPC分类号： G06F12/126

CPC分类号： G06F12/126

摘要： A method of managing cache partitions provides a first pointer for higher priority writes and a second pointer for lower priority writes, and uses the first pointer to delimit the lower priority writes. For example, locked writes have greater priority than unlocked writes, and a first pointer may be used for locked writes, and a second pointer may be used for unlocked writes. The first pointer is advanced responsive to making locked writes, and its advancement thus defines a locked region and an unlocked region. The second pointer is advanced responsive to making unlocked writes. The second pointer also is advanced (or retreated) as needed to prevent it from pointing to locations already traversed by the first pointer. Thus, the pointer delimits the unlocked region and allows the locked region to grow at the expense of the unlocked region.

公开(公告)号：EP1974255A1

公开(公告)日：2008-10-01

申请号：EP07710244.0

申请日：2007-01-22

申请人： QUALCOMM Incorporated

发明人： KOPEC, Brian Joseph ,  AUGSBURG, Victor Roberts ,  DIEFFENDERFER, James Norris ,  BRIDGES, Jeffrey Todd ,  SARTORIUS, Thomas Andrew

IPC分类号： G06F9/38

CPC分类号： G06F9/3861 ,  G06F12/1027

摘要： A processor having a multistage pipeline includes a TLB and a TLB controller. In response to a TLB miss signal, the TLB controller initiates a TLB reload, requesting address translation information from either a memory or a higher-level TLB, and placing that information into the TLB. The processor flushes the instruction having the missing virtual address, and refetches the instruction, resulting in re-insertion of the instruction at an initial stage of the pipeline above the TLB access point. The initiation of the TLB reload, and the flush/refetch of the instruction, are performed substantially in parallel, and without immediately stalling the pipeline. The refetched instruction is held at a point in the pipeline above the TLB access point until the TLB reload is complete, so that the refetched instruction generates a “hit” in the TLB upon its next access.

公开(公告)号：EP1941374A1

公开(公告)日：2008-07-09

申请号：EP06846129.2

申请日：2006-10-20

申请人： QUALCOMM Incorporated

发明人： AUGSBURG, Victor Roberts ,  SARTORIUS, Thomas Andrew ,  DIEFFENDERFER, James Norris ,  BRIDGES, Jeffrey Todd

IPC分类号： G06F12/10

CPC分类号： G06F12/1027 ,  G06F2212/681 ,  G06F2212/684

摘要： An apparatus includes a memory configured to store data, a lower level TLB, an upper level TLB, and a TLB controller. The lower level TLB and the upper level TLB are configured to store a plurality of entries, each of the entries containing an address translation information that allows a virtual address to be translated into a corresponding physical address. The TLB controller retrieves from a page table in the memory an address translation information for a desired virtual address, if the desired virtual address generates a TLB miss from the lower level TLB and from the upper level TLB, Using a single TLB write instruction, the TLB controller updates both the lower level TLB and the upper level TLB by writing the address translation information, retrieved from the page table, into the lower level TLB as well as into the upper level TLB.

公开(公告)号：EP1849061B1

公开(公告)日：2014-12-24

申请号：EP06735444.9

申请日：2006-02-16

申请人： QUALCOMM INCORPORATED

发明人： BRIDGES, Jeffrey Todd ,  AUGSBURG, Victor Roberts ,  DIEFFENDERFER, James Norris ,  SARTORIUS, Thomas Andrew

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/30043 ,  G06F9/30145 ,  G06F9/30189 ,  G06F9/3824 ,  G06F9/3832 ,  G06F9/3855

公开(公告)号：EP2118753B1

公开(公告)日：2013-07-10

申请号：EP08729314.8

申请日：2008-02-07

申请人： QUALCOMM Incorporated

发明人： KOPEC, Brian Joseph ,  AUGSBURG, Victor Roberts ,  DIEFFENDERFER, James Norris ,  SARTORIUS, Thomas Andrew

IPC分类号： G06F12/04 ,  G06F12/10

CPC分类号： G06F12/04 ,  G06F12/1027 ,  G06F2212/655 ,  Y02D10/13

摘要： Address translation performance within a processor is improved by identifying an address that causes a boundary crossing between different pages in memory and linking address translation information associated with both memory pages. According to one embodiment of a processor, the processor comprises circuitry configured to recognize an access to a memory region crossing a page boundary between first and second memory pages. The circuitry is also configured to link address translation information associated with the first and second memory pages. Thus, responsive to a subsequent access the same memory region, the address translation information associated with the first and second memory pages is retrievable based on a single address translation.