公开(公告)号：EP4388658A1

公开(公告)日：2024-06-26

申请号：EP22764595.9

申请日：2022-08-04

申请人： QUALCOMM INCORPORATED

发明人： AKHAVAN, Aram ,  YAMAMOTO, Kentaro ,  SUN, Lei ,  KIRAN, Ganesh

IPC分类号： H03F3/45 ,  H03F3/72

CPC分类号： H03F3/45183 ,  H03F3/72 ,  H03F3/45659 ,  H03F2200/29720130101 ,  H03F2200/51320130101 ,  H03F2203/4513420130101 ,  H03F2203/4563120130101 ,  H03F2203/4564120130101 ,  H03M1/164 ,  H03M1/124

公开(公告)号：EP4338282A1

公开(公告)日：2024-03-20

申请号：EP22716149.4

申请日：2022-03-21

申请人： QUALCOMM Incorporated

发明人： YAMAMOTO, Kentaro ,  AKHAVAN, Aram ,  KIRAN, Ganesh ,  SUN, Lei ,  DAGHER, Elias ,  ALLADI, Dinesh Jagannath

IPC分类号： H03F1/30 ,  H03F1/22 ,  H03F3/45 ,  H03F3/72 ,  H03M1/44

公开(公告)号：EP3353896A1

公开(公告)日：2018-08-01

申请号：EP16766119.8

申请日：2016-08-24

申请人： Qualcomm Incorporated

发明人： RAJAEE, Omid ,  HAN, Changsok ,  DAI, Liang ,  MIRHAJ, Seyed Arash ,  KIRAN, Ganesh

IPC分类号： H03M3/00 ,  H03M1/46 ,  H03M1/10

CPC分类号： H03M3/464 ,  H03M1/1023 ,  H03M1/46 ,  H03M3/37 ,  H03M3/422 ,  H03M3/47

摘要： Certain aspects of the present disclosure provide a delta-sigma modulator (DSM) using time-interleaved (TI) successive approximation register (SAR) analog-to-digital converters (ADCs). For example, two SAR ADCs may be configured to alternately sample and process an input signal and provide a feedback signal for the DSM using excess loop delay (ELD). In other aspects, the DSM may be implemented using a two-step SAR quantizer. For example, a first SAR ADC may sample an input signal to generate a most-significant bit (MSB) portion of an output of the DSM, while the second SAR ADC may subsequently sample a residue from the first SAR ADC conversion and generate a least-significant bit (LSB) portion of the output of the DSM. With these techniques, higher bandwidths may be obtained in high accuracy delta-sigma ADCs without using increased sampling rates.