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    Digital receiver and method
    1.
    发明公开
    Digital receiver and method 有权
    Digitalempfängerund Verfahren

    公开(公告)号：EP2523354A1

    公开(公告)日：2012-11-14

    申请号：EP12157021.2

    申请日：2004-03-31

    申请人： Nortel Networks Ltd.

    发明人： Morris, Bradley J. ,  Fuller, Arthur T. G.

    IPC分类号： H04B1/28 ,  H03M3/02

    CPC分类号： H04L27/22 ,  H03M3/462 ,  H03M3/47 ,  H03M7/3028 ,  H04B1/0007

    摘要： A receiver and method is provided for sigma-delta converting an RF signal to a digital signal and downconverting to a digital baseband signal. The RF signal is split into N phases, as can be accomplished using a sample and hold circuit, and each phase is digitized, as can be accomplished using an analog-to-digital (A/D) sigma-delta converter. Polyphase decimation techniques and demodulation are applied to the phased signals to generate a demodulated digital signal. The demodulated digital signal is further downconverted to the appropriate baseband signal.

    摘要翻译： 提供了一种接收机和方法，用于将RF信号转换成数字信号并下变频到数字基带信号的Σ-Δ。 RF信号被分为N个相位，可以使用采样和保持电路来实现，并且每个相位被数字化，如可以使用模数（A / D）Σ-Δ转换器来实现的。 将多相抽取技术和解调应用于相控信号以产生解调数字信号。 解调的数字信号进一步下变频到适当的基带信号。

    Voltage offset compensation method for time-interleaved multi-path analog-to-digital sigma-delta converters and respective circuit
    2.
    发明公开
    Voltage offset compensation method for time-interleaved multi-path analog-to-digital sigma-delta converters and respective circuit 有权
    Offsetspannungskompensationsverfahrenfürparallele zeitverschachtelte Analog-Digitalwandler sowie Schaltungdafür

    公开(公告)号：EP1401105A1

    公开(公告)日：2004-03-24

    申请号：EP02425563.0

    申请日：2002-09-17

    申请人： Siemens Mobile Communications S.p.A.

    发明人： Gatti, Umberto ,  Malcovati, Piero ,  Ferragina, Vincenzo ,  Fornasari, Andrea

    IPC分类号： H03M1/10

    CPC分类号： H03M3/384 ,  H03M3/47

    摘要： A multi-path time-interleaved analog-to-digital converter (MP-ADC) exploits an additional reference ADC cyclically connected in parallel to each ADC component part to be calibrated of the multi-path ADC, which can be of any kind, in particular sigma-delta, to whom conventional calibration techniques cannot be applied because of its stochastic behaviour. For each ADC component part the algebraic differences between successive digital outputs of the reference ADC and the ADC under calibration are forwarded to an accumulator circuit (13) which integrates them over a given time slot, obtaining a digital word (CH1',...,CH4') proportional to the difference between the offset of the two paths. A digital adder adds up the digital word so obtained to the output of the ADC component part under calibration multiplied by a scale factor which depends on the length of the given time slot. After a reasonable time the voltage offset of each individual path is proportional to the voltage offset of the only reference path, not necessarily zero. Optionally, the outputs of the digital adder are de-scaled by the same scale factor, restoring the original value. The time-interleaved ADC is continuously running and the voltage offset calibration is performed in background without affecting the normal operation (fig.7) .

    摘要翻译： 多路时间交织的模数转换器（MP-ADC）利用了一个额外的参考ADC，并行地并行地与待校准的多路径ADC的每个ADC组件部分并行地进行校准，该多路径ADC可以是任何类型的， 特定的Σ-Δ，由于其随机行为，传统的校准技术不能应用于此。 对于每个ADC组件部分，参考ADC和ADC在校准之间的连续数字输出之间的代数差异被转发到累加器电路（13），其在给定时隙上对它们进行积分，获得数字字（CH1'，...） ，CH4'）与两个路径的偏移之间的差成比例。 数字加法器将所获得的数字字相加在校准下的ADC分量部分的输出乘以比例因子，该比例因子取决于给定时隙的长度。 在合理的时间之后，每个单独路径的电压偏移量与唯一参考路径的电压偏移成比例，不一定为零。 可选地，数字加法器的输出通过相同的比例因子进行缩放，恢复原始值。 时间交织的ADC连续运行，并且在背景中执行电压偏移校准，而不影响正常操作（图7）。

    Method of performing A/D conversion, and an A/D converter
    5.
    发明公开
    Method of performing A/D conversion, and an A/D converter 审中-公开
    维也纳祖尔A / D-Wandlung和A / D-Wandler

    公开(公告)号：EP1164702A2

    公开(公告)日：2001-12-19

    申请号：EP01000207.9

    申请日：2001-06-12

    申请人： NOKIA MOBILE PHONES LTD.

    发明人： Aunio, Antti

    IPC分类号： H03M3/02

    CPC分类号： H03M3/47 ,  H03M3/418

    摘要： The invention relates to a method of performing AID conversion and to an A/D converter. The A/D conversion is performed by using at least two sigma-delta converters (50, 52) connected in cascade, the sigma-delta converters (50, 52) operating at a double sampling rate.

    摘要翻译： 本发明涉及一种执行AID转换和A / D转换器的方法。 A / D转换通过使用串联连接的至少两个Σ-Δ转换器（50,52）来执行，Σ-Δ转换器（50,52）以双倍采样率工作。

    INTERLEAVED MODULATOR
    7.
    发明公开
    INTERLEAVED MODULATOR 审中-公开
    交错调制器

    公开(公告)号：EP3158646A1

    公开(公告)日：2017-04-26

    申请号：EP15809124.9

    申请日：2015-06-19

    申请人： HRL Laboratories, LLC

    发明人： XU, Zhiwei A. ,  BARINGER, Cynthia D. ,  PETRE, Peter ,  HITKO, Donald A. ,  COSAND, Albert

    IPC分类号： H03M3/02

    CPC分类号： H03M3/47 ,  H03M1/066 ,  H03M3/358 ,  H03M3/37 ,  H03M3/454 ,  H03M3/46

    摘要： A delta sigma modulator which has improved the dynamic range. The ΔΣ modulator has a plurality of ADCs and a plurality of DACs, the plurality of ADCs and DACs are connected in a loop. The plurality of ADCs are coupled with an incoming analog signal. A clock generator provides a plurality of clock signals which control the plurality of ADCs and the plurality of DACs, the clock signals being offset relative to each other in the time domain thereby enabling each ADC in the plurality of ADCs one at a time and each DAC in the plurality of DACs one at a time so that the ΔΣ modulator processes data in the incoming analog signal in an interleaved fashion. The delta sigma modulator has an Nth order filter in a forward path of the loop.

    摘要翻译： 一种增加动态范围的Δ-Σ调制器。 ΔΣ调制器具有多个ADC和多个DAC，多个ADC和DAC连接成一个环路。 多个ADC与输入的模拟信号耦合。 时钟发生器提供控制多个ADC和多个DAC的多个时钟信号，时钟信号在时域中彼此相对偏移，从而使得多个ADC中的每个ADC一次一个，并且每个DAC 在多个DAC中一次一个，使得ΔΣ调制器以交错方式处理输入模拟信号中的数据。 Δ-Σ调制器在环路的正向路径中具有N阶滤波器。

    ANALOG-TO-DIGITAL CONVERTER WITH BANDPASS NOISE TRANSFER FUNCTION
    8.
    发明公开
    ANALOG-TO-DIGITAL CONVERTER WITH BANDPASS NOISE TRANSFER FUNCTION 审中-公开
    模拟数字万用表MITBANDPASSRAUSCHÜBERTRAGUNGSFUNKTION

    公开(公告)号：EP3148083A1

    公开(公告)日：2017-03-29

    申请号：EP16189537.0

    申请日：2016-09-19

    申请人： MediaTek Inc.

    发明人： Ho, Stacy ,  Tseng, Wei-Hsin

    IPC分类号： H03M3/00 ,  H04B1/00 ,  H04L5/00 ,  H04L27/26

    CPC分类号： H04L5/0041 ,  H03M1/0617 ,  H03M1/466 ,  H03M3/406 ,  H03M3/41 ,  H03M3/426 ,  H03M3/47 ,  H04B1/0075 ,  H04B1/123 ,  H04L5/001 ,  H04L27/2647

    摘要： Methods and apparatus for providing bandpass analog to digital conversion (ADC) in RF receiver circuitry of a wireless-communication device. The bandpass ADC includes first noise-shaping successive approximation register (NS-SAR) circuitry arranged in a first path and second NS-SAR circuitry arranged in a second path parallel to the first path, wherein the first and second NS-SAR circuitries are configured to alternately sample an analog input voltage at a particular sampling rate and to output a digital voltage at the particular sampling rate.

    摘要翻译： 用于在无线通信设备的RF接收机电路中提供带通模数转换（ADC）的方法和装置。 带通ADC包括布置在第一路径中的第一噪声整形逐次逼近寄存器（NS-SAR）电路和布置在平行于第一路径的第二路径中的第二NS-SAR电路，其中第一和第二NS-SAR电路被配置 交替地以特定采样率对模拟输入电压进行采样，并以特定采样率输出数字电压。

    DELTA-SIGMA ANALOG-TO-DIGITAL CONVERTER
    9.
    发明公开
    DELTA-SIGMA ANALOG-TO-DIGITAL CONVERTER 审中-公开
    经过Delta-Sigma模拟数字-WANDLER

    公开(公告)号：EP3078116A1

    公开(公告)日：2016-10-12

    申请号：EP14824111.0

    申请日：2014-12-04

    申请人： Murata Manufacturing Co., Ltd.

    发明人： AALTONEN, Lasse ,  SALO, Teemu ,  SILLANPÄÄ, Tero

    IPC分类号： H03M3/02

    CPC分类号： H03M3/368 ,  H03M3/466 ,  H03M3/47 ,  H03M3/474

    摘要： A delta-sigma analog-to-digital converter for use with multiplexed input channels. The delta-sigma analog-to-digital converter comprising at least one integrator that includes an operational amplifier, a memory element with a leakage preventing switch structure for each input channel and a reset switch element adapted to reset the operational amplifier between the input channels. The specific switch design prevents effectively channel to channel cross talk between multiplexed channels.