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公开(公告)号：EP2973704B1
公开(公告)日：2019-05-08
申请号：EP14713736.8
申请日：2014-03-10
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2.发明公开DEVICES AND METHODS FOR CALIBRATING AND OPERATING A SNAPBACK CLAMP CIRCUIT 审中-公开装置和方法，用于校准和操作电路后端SNAP CLAMP
公开(公告)号：EP2973703A1
公开(公告)日：2016-01-20
申请号：EP14713329.2
申请日：2014-03-06
CPC分类号： G05F1/10 , H01L27/0274 , H01L27/0277 , H01L27/0629 , H02H3/006 , H02H9/041 , H02H9/046
摘要： A device includes a snapback clamp circuit configured to clamp a supply voltage in response to the supply voltage exceeding a trigger voltage level. In at least one embodiment, the snapback clamp circuit includes a clamp transistor and a programmable resistance portion that is responsive to a control signal to calibrate the trigger voltage level. Alternatively or in addition, the snapback clamp circuit may include a programmable bias device configured to calibrate the trigger voltage level by biasing a gate terminal of the clamp transistor. In another particular embodiment, a method of calibrating a snapback clamp circuit is disclosed. In another particular embodiment, a method of operating an integrated circuit is disclosed.
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公开(公告)号：EP3050104A1
公开(公告)日：2016-08-03
申请号：EP14755744.1
申请日：2014-08-07
CPC分类号： H01L23/60 , H01L27/0285 , H01L27/0682 , H01L2924/0002 , H02H9/046 , H01L2924/00
摘要： A system interconnect includes a first resistor-capacitor (RC) clamp having a first RC time constant. The system interconnect also includes second RC clamps having a second RC time constant. The first and second RC clamps are arranged along the system interconnect. In addition, the first RC time constant is different from the second RC time constant.
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4.发明公开RADIO FREQUENCY INTEGRATED CIRCUIT (RFIC) CHARGED-DEVICE MODEL (CDM) PROTECTION 审中-公开被充电设备模型的集成电路中的高频保护
公开(公告)号：EP2973704A1
公开(公告)日：2016-01-20
申请号：EP14713736.8
申请日：2014-03-10
CPC分类号： H03F1/223 , H01L27/0255 , H02H9/046 , H03F1/523 , H03F3/193 , H03F2200/489
摘要： An apparatus is described. The apparatus includes an input device. The apparatus also includes a positive supply voltage pad. The apparatus further includes an input signal pad. The apparatus also includes a ground pad. The apparatus further includes charged-device model protection circuitry that protects the input device from electrostatic discharge. The charged-device model protection circuitry includes at least one of de-Q circuitry and a cascode device.
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公开(公告)号：EP3262753A1
公开(公告)日：2018-01-03
申请号：EP16704750.5
申请日：2016-01-27
发明人： YOUSSEF, Ahmed Abdel Monem , GUDEM, Prasad Srinivasa Siva , WORLEY, Eugene Robert , PAN, Dongling , CHANG, Li-Chung
CPC分类号： H03F1/523 , H01L27/0255 , H03F1/52 , H03F3/193 , H03F3/211 , H03F3/3016 , H03F3/68 , H03F2200/294 , H03F2200/441 , H03F2200/444 , H03F2200/451 , H03F2200/489 , H03F2203/21106
摘要： A CMOS amplifier including electrostatic discharge (ESD) protection circuits is disclosed. In one embodiment, the CMOS amplifier may include a PMOS transistor, a NMOS transistor, primary protection diodes, and one or more auxiliary protection diodes to limit a voltage difference between terminals of the CMOS amplifier. In some embodiments, the auxiliary protection diodes may limit the voltage difference between an input terminal of the CMOS amplifier and a supply voltage, the input terminal of the CMOS amplifier and ground, and the input terminal and the output terminal of the CMOS amplifier.
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6.发明公开
公开(公告)号：EP2904640A1
公开(公告)日：2015-08-12
申请号：EP13780016.5
申请日：2013-10-04
CPC分类号： H01L27/0285 , H02H9/046
摘要： Electrostatic discharge protection for Class D power amplifiers is disclosed. In an exemplary embodiment, an apparatus includes an amplifier having an output transistor coupled to an interface pad, a snapback supply clamp coupled across first and second supplies of the amplifier and configured to provide a clamp voltage across the first and second supplies during ESD event; and a trigger circuit coupled to the output transistor, the trigger circuit configured to detect the clamp voltage and to enable the output transistor to provide a discharge path from the interface pad to the second supply when the clamp voltage is detected.
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公开(公告)号：EP3437193A1
公开(公告)日：2019-02-06
申请号：EP17704366.8
申请日：2017-01-25
发明人： WORLEY, Eugene Robert , JALILIZEINALI, Reza , DUNDIGAL, Sreeker , CHEN, Wen-Yi , CHILLARA, Krishna Chaitanya , KANG, Taeghyun
IPC分类号： H03K19/003 , H03K19/0185
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公开(公告)号：EP3341966A1
公开(公告)日：2018-07-04
申请号：EP16760343.0
申请日：2016-08-26
CPC分类号： H02H9/046 , H01L23/48 , H01L23/60 , H01L23/62 , H01L27/0255 , H01L27/0292 , H01L27/0296 , H01L2224/16225 , H01L2924/15311 , H01L2924/181 , H02H9/044 , H01L2924/00012
摘要： An integrated circuit (IC) package includes a die, a package substrate coupled to the die, and a first electrostatic discharge (ESD) protection component coupled to the package substrate, where the first electrostatic discharge (ESD) protection component is configured to provide package level electrostatic discharge (ESD) protection. In some implementations, the first electrostatic discharge (ESD) protection component is embedded in the package substrate. In some implementations, the die includes an internal electrostatic discharge (ESD) protection component configured to provide die level electrostatic discharge (ESD) protection. In some implementations, the internal electrostatic discharge (ESD) protection component and the first electrostatic discharge (ESD) protection component are configured to provide cumulative electrostatic discharge (ESD) protection for the die.
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