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12 条记录 (耗时 0.01 秒)

    Method for forming barrier metal layers
    2.
    发明公开
    Method for forming barrier metal layers 失效
    Herstellungsverfahren von metallischen Barriere-Schichten。

    公开(公告)号：EP0545602A1

    公开(公告)日：1993-06-09

    申请号：EP92310724.7

    申请日：1992-11-24

    申请人： SGS-THOMSON MICROELECTRONICS, INC.

    发明人： Dixit, Girish A. ,  Liou, Fu-Tai ,  Wei, Che-Chia ,  Chen, Fusen

    IPC分类号： H01L21/285

    CPC分类号： H01L21/76856 ,  H01L21/76843 ,  H01L21/76877

    摘要： A method for forming interlevel contacts in integrated circuits includes the formation of a titanium nitride layer (26) prior to formation of an overlying conductive layer of a material such as polycrystalline silicon or a metal. In one approach, CVD titanium nitride (26) is deposited over a partially formed integrated circuit device and in a contact opening (20). The titanium nitride layer (26) is then exposed to an atmosphere containing oxygen, so that oxygen atoms diffuse into the titanium nitride layer (26). This may be done in conjunction with an annealing step. In another embodiment, layers of titanium (28) and titanium nitride (30) are sequentially sputtered onto the device. The nitride layer may then be exposed to an oxygen ambient, or the oxygen may be incorporated into the titanium nitride layer during the sputter deposition.

    摘要翻译： 在集成电路中形成层间接触的方法包括在形成诸如多晶硅或金属的材料的上覆导电层之前形成氮化钛层（26）。 在一种方法中，CVD氮化钛（26）沉积在部分形成的集成电路器件上和接触开口（20）中。 然后将氮化钛层（26）暴露于含氧的气氛中，使得氧原子扩散到氮化钛层（26）中。 这可以结合退火步骤来完成。 在另一个实施例中，钛（28）和氮化钛（30）的层依次溅射到器件上。 然后可以将氮化物层暴露于氧环境中，或者在溅射沉积期间可以将氧结合到氮化钛层中。

    Structure and method for contacts in CMOS devices
    3.
    发明公开
    Structure and method for contacts in CMOS devices 失效
    CMOS器件中的接触结构和方法

    公开(公告)号：EP0520658A3

    公开(公告)日：1993-01-20

    申请号：EP92305413.4

    申请日：1992-06-12

    申请人： SGS-THOMSON MICROELECTRONICS, INC.

    发明人： Chen, Fusen ,  Dixit, Girish ,  Bryant, Frank Randolph

    IPC分类号： H01L21/3105 ,  H01L21/311

    CPC分类号： H01L21/76802 ,  Y10S148/133

    摘要： A metal oxide layer (24) is then formed over the source/drain region (22). An insulating layer (26) is formed over the metal oxide layer (24). A photoresist layer (28) is formed over the insulating layer (26), and patterned to form an opening (30), exposing a portion of the insulating layer (26). The insulating layer (26) is then etched to expose a portion of the metal oxide layer (24). The photoresist layer (28) is removed and the insulating layer (26) is reflowed. The exposed portion of the metal oxide layer (24) is removed to expose a portion of the active region (22).

    Local interconnect for integrated circuits
    5.
    发明公开
    Local interconnect for integrated circuits 失效
    Lokalverbindungenfürintegrierte Schaltungen。

    公开(公告)号：EP0517368A2

    公开(公告)日：1992-12-09

    申请号：EP92303974.7

    申请日：1992-05-01

    申请人： SGS-THOMSON MICROELECTRONICS, INC.

    发明人： Chen, Fusen ,  Liou, Fu-Tai ,  Dixit, Girish

    IPC分类号： H01L21/90 ,  H01L23/485 ,  H01L21/3205

    CPC分类号： H01L23/53257 ,  H01L21/76889 ,  H01L2924/0002 ,  Y10S148/019 ,  Y10S257/915 ,  H01L2924/00

    摘要： A method for fabrication of local interconnects in an integrated circuit, and an integrated circuit formed according to the same, is disclosed. According to the disclosed embodiment, a first and a second conductive structure are formed over the integrated circuit. An insulating layer (28) is formed over the integrated. A first photoresist layer is formed over the insulating layer, patterned and developed. The insulating layer is etched to expose selected regions of the first and second conductive structures. A refractory metal layer (30) is formed over the integrated circuit. A barrier layer (32) is formed over the refractory metal layer, and optionally a refractory metal silicide layer (34) is formed over the barrier layer. A second photoresist layer is formed over the barrier layer, patterned and developed. The refractory metal layer and barrier layer, and the refractory metal silicide layer if formed, are etched to define a conductive interconnect between the exposed selected regions of the first and second conductive structures.

    摘要翻译： 公开了一种用于制造集成电路中的局部互连的方法，以及根据该集成电路形成的集成电路。 根据所公开的实施例，在集成电路上形成第一和第二导电结构。 在整合上形成绝缘层。 第一光致抗蚀剂层形成在绝缘层上，被图案化和显影。 蚀刻绝缘层以暴露第一和第二导电结构的选定区域。 在集成电路上形成难熔金属层。 阻挡层形成在难熔金属层的上方，并且任选地在阻挡层上形成难熔金属硅化物层。 第二光致抗蚀剂层形成在阻挡层上，被图案化和显影。 难熔金属层和阻挡层以及如果形成的难熔金属硅化物层被蚀刻以在第一和第二导电结构的暴露的选定区域之间限定导电互连。

    Structure and method for contacts in CMOS devices
    6.
    发明公开
    Structure and method for contacts in CMOS devices 失效
    在CMOS-Schaltungen的Struktur und Herstellungsverfahren von Kontakten。

    公开(公告)号：EP0520658A2

    公开(公告)日：1992-12-30

    申请号：EP92305413.4

    申请日：1992-06-12

    申请人： SGS-THOMSON MICROELECTRONICS, INC.

    发明人： Chen, Fusen ,  Dixit, Girish ,  Bryant, Frank Randolph

    IPC分类号： H01L21/3105 ,  H01L21/311

    CPC分类号： H01L21/76802 ,  Y10S148/133

    摘要： A metal oxide layer (24) is then formed over the source/drain region (22). An insulating layer (26) is formed over the metal oxide layer (24). A photoresist layer (28) is formed over the insulating layer (26), and patterned to form an opening (30), exposing a portion of the insulating layer (26). The insulating layer (26) is then etched to expose a portion of the metal oxide layer (24). The photoresist layer (28) is removed and the insulating layer (26) is reflowed. The exposed portion of the metal oxide layer (24) is removed to expose a portion of the active region (22).

    摘要翻译： 然后在源/漏区（22）上形成金属氧化物层（24）。 绝缘层（26）形成在金属氧化物层（24）的上方。 在所述绝缘层（26）之上形成光致抗蚀剂层（28），并且被图案化以形成开口（30），暴露所述绝缘层（26）的一部分。 然后蚀刻绝缘层（26）以暴露金属氧化物层（24）的一部分。 去除光致抗蚀剂层（28）并且覆盖绝缘层（26）。 去除金属氧化物层（24）的暴露部分以暴露活性区域（22）的一部分。

    Dynamic random access memory cell
    7.
    发明公开
    Dynamic random access memory cell 失效
    Dynamische Speicherzelle mit wahlfreiem Zugriff。

    公开(公告)号：EP0508760A1

    公开(公告)日：1992-10-14

    申请号：EP92303134.8

    申请日：1992-04-08

    申请人： SGS-THOMSON MICROELECTRONICS, INC.

    发明人： Deptuch, Roland G. ,  Chen, Fusen

    IPC分类号： H01L27/108

    CPC分类号： H01L27/10808

    摘要： A dynamic random access memory cell includes a metal capacitor above an access transistor. Tungsten plugs are used to contact an active area of a device substrate. Tantalum is used for the charge storage plate of the capacitor, and oxidized to provide the capacitor dielectric. A tungsten reference plate can be deposited over the charge storage plate and dielectric to provide a common reference plate for all memory cells on the device. The tantalum oxide dielectric is formed on sidewalls of the charge storage plate, so that the capacitance of the capacitor can be increased by making the charge storage plate taller. This design allows overall cell size to shrink while maintaining adequate charge storage capacitance.

    摘要翻译： 动态随机存取存储单元包括存取晶体管之上的金属电容器。 钨插头用于接触器件基板的有源区。 钽用于电容器的电荷存储板，并被氧化以提供电容器电介质。 可以在电荷存储板和电介质上沉积钨参考板，以为器件上的所有存储器单元提供公共参考板。 氧化钽电介质形成在电荷存储板的侧壁上，从而可以通过使电荷存储板更高而增加电容器的电容。 该设计允许整体电池尺寸缩小同时保持足够的电荷存储电容。

    Method for reducing the surface reflectance of a metal layer during semiconductor processing
    9.
    发明公开
    Method for reducing the surface reflectance of a metal layer during semiconductor processing 失效
    用于半导体装置的处理过程中降低金属层的表面反射的方法。

    公开(公告)号：EP0367511A2

    公开(公告)日：1990-05-09

    申请号：EP89311124.5

    申请日：1989-10-27

    申请人： SGS-THOMSON MICROELECTRONICS, INC.

    发明人： Chen, Fusen ,  Lin, Yih-Shung ,  Liou, Fu-Tai

    IPC分类号： H01L21/00 ,  H01L21/31

    CPC分类号： H01L21/0276 ,  H01L21/321 ,  Y10S148/138 ,  Y10S148/158 ,  Y10S438/952

    摘要： The method for reducing the surface reflectance of the metal layer during semiconductor processing includes the step of roughening the surface of a metal layer prior to forming the photoresist thereon. The roughened surface reduces reflections that can cause metal notching effects. The step of roughening the surface includes depositing a layer (34) of aluminum which is substantially thinner than the thickness of the primary metal layer by a sputtering process.

    摘要翻译： 用于半导体加工过程中减少金属层的表面反射率的方法，包括在其光致抗蚀剂形成之前的金属层的表面粗糙化的步骤。 粗糙化的表面减少反射做可能会导致金属开槽的效果。 使表面粗糙化的步骤包括沉积的铝的所有的层（34），其基本上大于由溅射工艺在主金属层的厚度薄。