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    BICMOS transconductor differential stage for high-frequency filters
    1.
    发明公开
    BICMOS transconductor differential stage for high-frequency filters 失效
    用于高频滤波器的BICMOS跨导差分级

    公开(公告)号：EP0810723A1

    公开(公告)日：1997-12-03

    申请号：EP96830311.5

    申请日：1996-05-31

    申请人： SGS-THOMSON MICROELECTRONICS s.r.l. ,  CO.RI.M.ME.

    发明人： Pisati, Valerio ,  Alini, Roberto ,  Cosentino, Gaetano ,  Vai, Gianfranco

    IPC分类号： H03H1/00 ,  H03F3/45 ,  H03F3/72

    CPC分类号： H03F3/72 ,  H03F3/45286 ,  H03F2203/45302 ,  H03F2203/45304 ,  H03F2203/45371 ,  H03F2203/45396 ,  H03F2203/45506

    摘要： A BiCMOS Transconductor differential stage (10) for high frequency filters comprises an input circuit portion having signal inputs (IN+,IN-) and comprising a pair of MOS transistors (M1,M2) having their respective gate terminals (G1,G2) corresponding to the signal inputs as well as an output circuit portion having signal outputs (OUT-,OUT+) and comprising a pair of two-pole transistors (Q1,Q2) connected together with a common base in a circuit node (B) and inserted between inputs (IN+,IN-) and outputs (OUT-,OUT+) in cascode configuration. The stage (10) in accordance with the present invention calls for a switching device (3) associated with at least one of said added two-pole transistors (Q1,Q2) to change the connections between the parasite capacitors present in the transconductor stage. The switching device (3) also comprises at least one added two-pole transistor (Q1x, Q2x) connected in a removable manner in parallel with the corresponding two-pole cascode transistor (Q1,Q2).
    In a variant embodiment there are also provided respective added MOS transistors (M1x,M2x) connected in parallel with the MOS transistors (M1,M2) of the input portion to change the ratio W:L of each of the input transistors (M1,M2).

    摘要翻译： 一种用于高频滤波器的BiCMOS跨导差分级（10）包括具有信号输入端（IN +，IN-）并包括一对MOS晶体管（M1，M2）的输入电路部分，所述一对MOS晶体管的各自的栅极端子（G1，G2） 信号输入端以及具有信号输出端（OUT-，OUT +）的输出电路部分，并且包括在电路节点（B）中用公共基极连接在一起的一对双极晶体管（Q1，Q2），并插入在输入端 （IN +，IN-）和输出（OUT-，OUT +）级联配置。 根据本发明的级（10）需要与所述增加的双极晶体管（Q1，Q2）中的至少一个相关联的开关器件（3）改变跨导级中存在的寄生电容器之间的连接。 开关器件（3）还包括至少一个与对应的双极共源共栅晶体管（Q1，Q2）并联连接的增加的双极晶体管（Q1x，Q2x）。 在变型实施例中，还提供了与输入部分的MOS晶体管（M1，M2）并联连接的相应增加的MOS晶体管（M1x，M2x），以改变每个输入晶体管（M1，M2）的比率W:L ）。

    Control loop for reducing the time of response of a tuner-AGC of a superheterodyne receiver and relative leading edge differentiating circuit used in the control loop
    2.
    发明公开
    Control loop for reducing the time of response of a tuner-AGC of a superheterodyne receiver and relative leading edge differentiating circuit used in the control loop 失效
    用于减少超外差接收机调谐器的自动增益控制的响应时间和相关联的用于边缘相对上升微分电路的控制回路。

    公开(公告)号：EP0439435A2

    公开(公告)日：1991-07-31

    申请号：EP91830006.2

    申请日：1991-01-17

    申请人： SGS-THOMSON MICROELECTRONICS s.r.l.

    发明人： Gornati, Silvano ,  Betti, Giorgio ,  Sacchi, Fabrizio ,  Vai, Gianfranco ,  Zuffada, Maurizio

    IPC分类号： H03G3/30

    CPC分类号： H03G3/3068

    摘要： In a dynamic automatic loop for control of the overall gain of an input circuit of a superheterodyne receiver, the response time of the HF-AGC circuit of the TUNER, in response to the action of the TUNER DELAY circuit activated by the IF-AGC in the case of autonomously uncontrollable abrupt increases in the level of the antenna signal from the same HF-AGC of the TUNER, is markedly reduced using an additional TUNER DELAY PLUS circuit able to absorb for a determined interval of time, a discharge current from the storage capacitor the control voltage of the HF-AGC in addition to the discharge current absorbed by the existing TUNER DELAY circuit. The relevant intensity of this additional discharge current and its duration are optimized by way of suitable circuital arrangements in the design of said TUNER DELAY PLUS circuit. The response time is reduced without modifying the time constant of the HF-AGC, which cannot be freely reduced because of inter- and cross-modulation problems.

    摘要翻译： 在响应于TUNER延迟电路由IF AGC活化作用的动态自动环路用于超外差式接收机中，调谐器的RF AGC电路的响应时间，的输入电路的总增益的控制 自主地不可控的情况下，在从调谐器的相同的RF AGC的天线信号的电平突然增加，显着地使用附加的TUNER延迟加上电路能够吸收的时间确定的开采间隔，从所述存储的放电电流的减少 电容器控制所述RF AGC的电压除了由现有的TUNER延迟电路所吸收的放电电流。 该附加的放电电流和它的持续时间的相关强度是通过在所述调谐器延迟加上电路的设计合适circuital安排方式优化。 响应时间，而无需修改RF AGC，不能自由地减少由于间和交叉调制问题的时间常数减小。

    Transconductor stage with controlled gain
    3.
    发明公开
    Transconductor stage with controlled gain 失效
    Transkonduktanzstufe mit gesteuerterVerstärkung

    公开(公告)号：EP0695030A1

    公开(公告)日：1996-01-31

    申请号：EP94830390.4

    申请日：1994-07-29

    申请人： SGS-THOMSON MICROELECTRONICS S.r.l.

    发明人： Pisati, Valerio ,  Alini, Roberto ,  Castello, Rinaldo ,  Vai, Gianfranco

    IPC分类号： H03G1/00 ,  H03F1/08 ,  H03H11/04

    CPC分类号： H03F3/45883 ,  H03F3/45286 ,  H03F3/45807 ,  H03F2203/45648 ,  H03G1/0023

    摘要： A controlled gain transconductor (20) which comprises a transconductance stage (3) having at least two input terminals (I1, I2) and at least two output terminals (O1, O2), an active load (4) connected to the output terminals of the transconductance stage and a control circuit (5) for the active load (4) conneccted between said output terminals (O1, O2) and the active load (4).
    Also provided is a circuit portion (10) being a replica of the transconductance stage (3), the active load (4) and the control circuit (5). This replicated portion (10) has an output connected to the control circuit (5) of the transconductor (20) to provide a predetermined voltage value (Vc) required for adjusting the DC gain of the device.

    摘要翻译： 一种受控增益跨导体（20），包括具有至少两个输入端（I1，I2）和至少两个输出端（O1，O2）的跨导级（3），连接到输出端 所述跨导级和用于所述输出端子（O1，O2）和所述有源负载（4）之间连接的有源负载（4）的控制电路（5）。 还提供了作为跨导级（3），有源负载（4）和控制电路（5）的复制品的电路部分（10）。 该复制部分（10）具有连接到跨导体（20）的控制电路（5）的输出端，以提供调节器件的直流增益所需的预定电压值（Vc）。

    A circuit device for phasing an oscillator
    7.
    发明公开
    A circuit device for phasing an oscillator 失效
    一种用于激励振荡器的电路装置

    公开(公告)号：EP0492338A3

    公开(公告)日：1993-10-27

    申请号：EP91121516.8

    申请日：1991-12-16

    申请人： SGS-THOMSON MICROELECTRONICS S.r.l.

    发明人： Vai, Gianfranco ,  Zuffada, Maurizio ,  Sacchi, Fabrizio ,  Moloney, David ,  Betti, Giorgio

    IPC分类号： H03K3/282

    CPC分类号： H03K3/2821

    摘要： A circuit device (1) for phasing an oscillator (2), which comprises a multivibrator (3) having a transistor pair (Q1,Q2) with the emitters (E1,E2) coupled through a capacitor (C), comprises a normally open electronic switch (SW) controlled by a drive signal (IN) to close and inhibit the oscillator (2). This switch connects a voltage divider to the base of a transistor (Q7) connected to one (E2) of the emitters to interrupt the loop positive feedback of the oscillator (2) upon the voltage across the capacitor reaching a predetermined value.

    Integrated circuit for generating a temperature independent current proportional to the voltage difference between a signal and a reference voltage
    9.
    发明公开
    Integrated circuit for generating a temperature independent current proportional to the voltage difference between a signal and a reference voltage 失效
    集成电路，用于产生独立的电流的温度成比例的信号和参考电压之间的电压差。

    公开(公告)号：EP0490016A1

    公开(公告)日：1992-06-17

    申请号：EP90830579.0

    申请日：1990-12-12

    申请人： SGS-THOMSON MICROELECTRONICS S.r.l.

    发明人： Sacchi, Fabrizio ,  Zuffada, Maurizio ,  Vai, Gianfranco ,  Moloney, David

    IPC分类号： H03G1/00 ,  H03G1/04 ,  G05F3/22

    CPC分类号： H03G1/04 ,  G05F3/225 ,  H03G1/0023

    摘要： A circuit particularly useful in AGC systems, produces an output current (I OUT ) which is proportional to the difference between a signal voltage (V AGC ) and a reference voltage (V R ) which is practically independent of temperature, by being a function of a ratio among actual values of integrated resistances and of a ratio among substantially temperature-stable voltages. The effects of temperature dependent value of integrated resistances and of temperature-dependent electrical characteristics of integrated semiconductor devices are compensated in order to produce the desired temperature-independent output current which may usefully be utilized for implementing an automatic gain control.

    摘要翻译： 所有这实际上与温度无关，通过作为比之间的函数的输出电流（I OUT）的所有成比例的信号电压（V AGC）和参考电压（VR）之间的差的电路中的AGC系统是特别有用的，可生产 的集成termoresistencias和基本上温度稳定的电压之间的比率的实际值。 的集成termoresistencias和的集成半导体器件的依赖于温度的电特性的温度依赖值的影响，以便产生所需的温度无关的输出电流可以有用地用于实施的自动增益控制进行补偿。

    An electronic comparator device with hysteresis
    10.
    发明公开
    An electronic comparator device with hysteresis 失效
    具有HYSTERESIS的电子比较器装置

    公开(公告)号：EP0427016A3

    公开(公告)日：1992-02-26

    申请号：EP90119873.9

    申请日：1990-10-17

    申请人： SGS-THOMSON MICROELECTRONICS S.r.l.

    发明人： Sacchi, Fabrizio ,  Lietar, Loic ,  Vai, Gianfranco ,  Betti, Giorgio

    IPC分类号： H03K3/023

    CPC分类号： H03K3/02337

    摘要： An electronic comparator device (1) with hysteresis, being of a type which comprises a differential cell (2) having a signal input (IN), an output (OUT), and a threshold input (S), further comprises a second differential cell (9) having one input (B9) connected to said output (OUT) and the other input (B10) connected to a controlling circuit portion (10) which has an output (E11) connected to the threshold input (S) to reduce the threshold voltage value (Vs) stepwise on the first change-over of the output (OUT) of the comparator (1).