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    SILICON PHOTONICS MODULATOR DRIVER
    2.
    发明公开
    SILICON PHOTONICS MODULATOR DRIVER 审中-公开
    硅光子调制器驱动程序

    公开(公告)号：EP3210301A1

    公开(公告)日：2017-08-30

    申请号：EP15787384.5

    申请日：2015-10-15

    Applicant: Cisco Technology, Inc.

    Inventor： LAKSHIMIKUMAR, Kadaba ,  APPEL, Craig

    IPC: H03F3/45 ,  H03F1/08

    CPC classification number: H03F3/08 ,  H03F1/0205 ,  H03F1/086 ,  H03F3/45076 ,  H03F3/45183 ,  H03F3/45659 ,  H03F2200/135 ,  H03F2200/75 ,  H03F2203/45026 ,  H03F2203/45082 ,  H03F2203/45088 ,  H03F2203/45116 ,  H03F2203/45208 ,  H03F2203/45221 ,  H03F2203/45336 ,  H03F2203/45402 ,  H03F2203/45418 ,  H03F2203/45434 ,  H03F2203/45436 ,  H03F2203/45481 ,  H03F2203/45594 ,  H03F2203/45604 ,  H03F2203/45642 ,  H03F2203/45648 ,  H03F2203/45664

    Abstract: Embodiments generally relate to a conversion arrangement, a driver arrangement, and a method of producing a complementary complementary metal-oxide-semiconductor (CMOS) output signal for driving a modulator device. The conversion arrangement includes a differential amplifier configured to produce a first amplified signal based on the differential input signal, and at least two transimpedance amplifiers (TIAs) coupled with respective outputs of the differential amplifier and configured to produce a second amplified signal based on the first amplified signal. Respective bias voltages for the TIAs are based on the first amplified signal. The conversion arrangement further includes a common-mode feedback arrangement coupled with outputs of the TIAs and configured to control the first amplified signal based on the second amplified signal, thereby controlling the bias voltages, wherein the complementary CMOS output signal is based on the second amplified signal.

    Abstract translation: 实施例一般涉及转换装置，驱动器装置以及产生用于驱动调制器装置的互补互补金属氧化物半导体（CMOS）输出信号的方法。 该转换装置包括被配置为基于差分输入信号产生第一放大信号的差分放大器以及与差分放大器的相应输出耦合并且被配置为基于第一放大信号产生第一放大信号的至少两个跨导放大器（TIA） 放大信号。 TIA的相应偏置电压基于第一放大信号。 该转换装置进一步包括共模反馈装置，该共模反馈装置与TIA的输出耦合并被配置为基于第二放大信号来控制第一放大信号，由此控制偏置电压，其中互补CMOS输出信号基于第二放大 信号。

    Low-noise high efficiency bias generation circuits and method
    4.
    发明公开
    Low-noise high efficiency bias generation circuits and method 审中-公开
    低噪音，高效率的偏置电压发生电路和方法

    公开(公告)号：EP2346169A3

    公开(公告)日：2013-11-20

    申请号：EP11154275.9

    申请日：2009-07-17

    Applicant: PEREGRINE SEMICONDUCTOR CORPORATION

    Inventor： Kim, Tae Youn ,  Englekirk, Robert Mark ,  Kelly, Dylan J.

    IPC: H03K17/00 ,  H03K17/14

    CPC classification number: H03F1/26 ,  H02M3/07 ,  H03F3/45183 ,  H03F3/45237 ,  H03F3/45475 ,  H03F3/45659 ,  H03F2200/453 ,  H03F2200/456 ,  H03F2200/474 ,  H03F2203/45138 ,  H03F2203/45188 ,  H03F2203/45366 ,  H03F2203/45418 ,  H03F2203/45424 ,  H03F2203/45471 ,  H03F2203/45642 ,  H03H11/245 ,  H03K17/145

    Abstract: A bias generation method or apparatus defined by any one or any practical combination of numerous features that contribute to low noise and/or high efficiency biasing, including: having a charge pump control clock output with a waveform having limited harmonic content or distortion compared to a sine wave; having a ring oscillator to generating a charge pump clock that includes inverters current limited by cascode devices and achieves substantially rail-to-rail output amplitude; having a differential ring oscillator with optional startup and/or phase locking features to produce two phase outputs suitably matched and in adequate phase opposition; having a ring oscillator of less than five stages generating a charge pump clock; capacitively coupling the clock output(s) to some or all of the charge transfer capacitor switches; biasing an FET, which is capacitively coupled to a drive signal, to a bias voltage via an "active bias resistor" circuit that conducts between output terminals only during portions of a waveform appearing between the terminals, and/or wherein the bias voltage is generated by switching a small capacitance at cycles of said waveform. A threshold voltage bias voltage generation circuit may A charge pump for the bias generation may include a regulating feedback loop including an OTA that is also suitable for other uses, the OTA having a ratio-control input that controls a current mirror ratio in a differential amplifier over a continuous range, and optionally has differential outputs including an inverting output produced by a second differential amplifier that optionally includes a variable ratio current mirror controlled by the same ratio-control input. The ratio-control input may therefore control a common mode voltage of the differential outputs of the OTA. A control loop around the OTA may be configured to control the ratio of one or more variable ratio current mirrors, which may particularly control the output common mode voltage, and may control it such that the inverting output level tracks the non-inverting output level to cause the amplifier to function as a high-gain integrator.

    Receiving circuit
    6.
    发明公开
    Receiving circuit 审中-公开
    Empfangsschaltung

    公开(公告)号：EP2346161A1

    公开(公告)日：2011-07-20

    申请号：EP10196807.1

    申请日：2010-12-23

    Applicant: Renesas Electronics Corporation

    Inventor： Nakamura, Wataru

    IPC: H03F1/02 ,  H03F3/45

    CPC classification number: H03F3/45475 ,  H03F1/0266 ,  H03F3/45959 ,  H03F2200/27 ,  H03F2200/282 ,  H03F2200/294 ,  H03F2200/451 ,  H03F2200/471 ,  H03F2203/45418 ,  H03F2203/45424 ,  H03F2203/45434 ,  H03F2203/45541 ,  H03F2203/45578 ,  H03F2203/45581 ,  H03F2203/45588 ,  H03F2203/45594 ,  H03F2203/45596

    Abstract: A receiving circuit in accordance with an exemplary aspect of the present invention includes a first voltage-dividing circuit that outputs a first input signal obtained by voltage division of one of differential signals based on the resistance ratio between first and second resistors, a second voltage-dividing circuit that outputs a second input signal obtained by voltage division of the other of the differential signals based on the resistance ratio between third and fourth resistors, a differential amplifier that amplifies the differential component between the first and second input signals, a common-mode voltage detection circuit that detects the common-mode voltage of the differential signals, and a bias voltage switching circuit that switches the voltage value of a bias voltage based on the common-mode voltage.

    Abstract translation: 根据本发明的示例性方面的接收电路包括：第一分压电路，其基于第一和第二电阻器之间的电阻比，输出由差分信号中的一个分压得到的第一输入信号;第二电压 - 分压电路，其输出基于第三和第四电阻器之间的电阻比的另一个差分信号的分压获得的第二输入信号;放大第一和第二输入信号之间的差分分量的差分放大器;共模 检测差分信号的共模电压的电压检测电路，以及基于共模电压来切换偏置电压的电压值的偏置电压切换电路。

    LOW-NOISE HIGH EFFICIENCY BIAS GENERATION CIRCUITS AND METHOD
    7.
    发明公开
    LOW-NOISE HIGH EFFICIENCY BIAS GENERATION CIRCUITS AND METHOD 审中-公开
    低噪声高效率偏置电路和方法

    公开(公告)号：EP2311184A2

    公开(公告)日：2011-04-20

    申请号：EP09798318.3

    申请日：2009-07-17

    Applicant: PEREGRINE SEMICONDUCTOR CORPORATION

    Inventor： KIM, Tae Youn ,  ENGLEKIRK, Robert Mark ,  KELLY, Dylan, J.

    IPC: H03F1/26

    CPC classification number: H03F1/26 ,  H02M3/07 ,  H03F3/45183 ,  H03F3/45237 ,  H03F3/45475 ,  H03F3/45659 ,  H03F2200/453 ,  H03F2200/456 ,  H03F2200/474 ,  H03F2203/45138 ,  H03F2203/45188 ,  H03F2203/45366 ,  H03F2203/45418 ,  H03F2203/45424 ,  H03F2203/45471 ,  H03F2203/45642 ,  H03H11/245 ,  H03K17/145

    Abstract: A bias generation method or apparatus defined by any one or any practical combination of numerous features that contribute to low noise and/or high efficiency biasing, including: having a charge pump control clock output with a waveform having limited harmonic content or distortion compared to a sine wave; having a ring oscillator to generating a charge pump clock that includes inverters current limited by cascode devices and achieves substantially rail-to-rail output amplitude; having a differential ring oscillator with optional startup and/or phase locking features to produce two phase outputs suitably matched and in adequate phase opposition; having a ring oscillator of less than five stages generating a charge pump clock; capacitively coupling the clock output(s) to some or all of the charge transfer capacitor switches; biasing an FET, which is capacitively coupled to a drive signal, to a bias voltage via an "active bias resistor" circuit that conducts between output terminals only during portions of a waveform appearing between the terminals, and/or wherein the bias voltage is generated by switching a small capacitance at cycles of said waveform. A threshold voltage bias voltage generation circuit may A charge pump for the bias generation may include a regulating feedback loop including an OTA that is also suitable for other uses, the OTA having a ratio-control input that controls a current mirror ratio in a differential amplifier over a continuous range, and optionally has differential outputs including an inverting output produced by a second differential amplifier that optionally includes a variable ratio current mirror controlled by the same ratio-control input. The ratio-control input may therefore control a common mode voltage of the differential outputs of the OTA. A control loop around the OTA may be configured to control the ratio of one or more variable ratio current mirrors, which may particularly control the output common mode voltage, and may control it such that the inverting output level tracks the non-inverting output level to cause the amplifier to function as a high-gain integrator.

    Abstract translation: 由有助于低噪声和/或高效率偏置的众多特征中的任何一个或任何实际组合定义的偏置生成方法或装置包括：具有电荷泵控制时钟输出，其具有与具有有限谐波含量或失真的波形相比 正弦波; 具有用于产生电荷泵时钟的环形振荡器，所述电荷泵时钟包括由共源共栅器件限制的电流的逆变器并且实质上实现轨到轨输出幅度; 具有差分环形振荡器，其具有可选的启动和/或锁相特征以产生适当匹配且处于适当反相的两相输出; 具有产生电荷泵时钟的小于五级的环形振荡器; 将时钟输出电容耦合到一些或全部电荷转移电容器开关; 和/或其中产生偏置电压的偏置电压经由仅在出现在端子之间的波形的部分期间在输出端子之间导通的“有源偏置电阻器”电路来偏置与驱动信号电容耦合的FET到偏置电压 通过在所述波形的周期切换小电容。 阈值电压偏置电压产生电路可以用于偏置产生的电荷泵可以包括调节反馈环路，该调节反馈环路包括也适用于其他用途的OTA，该OTA具有比率控制输入，该比例控制输入控制差分放大器中的电流镜像比 并且可选地具有包括由第二差分放大器产生的反相输出的差分输出，所述第二差分放大器可选地包括由相同比率控制输入控制的可变比率电流镜。 比率控制输入因此可以控制OTA的差分输出的共模电压。 围绕OTA的控制回路可以被配置为控制一个或多个可变比率电流镜的比率，其可以特别地控制输出共模电压，并且可以控制它以使得反相输出电平跟踪非反相输出电平到 使放大器起到高增益积分器的作用。

    DIFFERENTIELLER, KOMPLEMENTÄRER VERSTÄRKER
    9.
    发明授权
    DIFFERENTIELLER, KOMPLEMENTÄRER VERSTÄRKER 有权
    差动互补放大器

    公开(公告)号：EP1310043B1

    公开(公告)日：2006-01-04

    申请号：EP01967005.8

    申请日：2001-08-15

    Applicant: Infineon Technologies AG

    Inventor： SCHROEDINGER, Karl ,  STIMMA, Jaro

    IPC: H03F3/45

    CPC classification number: H03F3/45251 ,  H03F3/45237 ,  H03F3/4565 ,  H03F2203/45418 ,  H03F2203/45458 ,  H03F2203/45476 ,  H03F2203/45631

    Abstract: The invention relates to a differential complementary amplifier that comprises two MOSFET amplifier branches (1, 2). According to the invention, the second amplifier branch (2) is operated in the opposite sense relative to the first amplifier branch (1). The outputs of the two amplifier branches (1, 2) form a differential output and are interlinked in a node (A) via a load resistor (R1, R2). The operating point of the two amplifier branches (1, 2) is adjusted via the voltage applied to said node (A). The invention provides a fully differential, highly symmetrical amplifier circuit in which both amplifier branches are used as amplifiers and a signal is derived from said amplifier branches to stabilize the operating point.

    Wideband common-mode regulation circuit
    10.
    发明公开
    Wideband common-mode regulation circuit 审中-公开
    Breitband-Gleichtaktregler

    公开(公告)号：EP1434348A1

    公开(公告)日：2004-06-30

    申请号：EP03290814.7

    申请日：2003-03-31

    Applicant: ALCATEL

    Inventor： Gajdardziew Radelinow, Andrzej

    IPC: H03K5/24 ,  H03F3/45 ,  H04L25/02

    CPC classification number: H04L25/0274 ,  H03F1/08 ,  H03F3/45475 ,  H03F3/45479 ,  H03F3/45928 ,  H03F3/45964 ,  H03F2200/36 ,  H03F2203/45418 ,  H03F2203/45616 ,  H03K5/003 ,  H04L25/028

    Abstract: A wideband common-mode regulation circuit for coupling a differential amplifier, or more particularly a Low Voltage Differential Signaling driver LVDS, to a load generally constituted by a telecommunication transmission line. The regulation circuit only comprises a first resistive pair (R1, R2) to sense the common-mode voltage at the differential input terminals (INP, INN), a second resistive pair (R3, R4) to force the voltage across the load to a predetermined value, and an active device (OTA, INV) coupled between the junction points of the first and the second resistive pairs. The active device is an Operational Transconductance Amplifier (OTA) or, preferably, an inverter (INV). Owing to reduced number of non-dominant poles in the common-mode open-loop transfer characteristic, this regulation circuit provides common-mode loop stability for wide common-mode loop bandwidth.

    Abstract translation: 一种宽带共模调节电路，用于将差分放大器，或更具体地，低电压差分信号驱动器LVDS耦合到通常由电信传输线构成的负载。 调节电路仅包括用于感测差分输入端（INP，INN）上的共模电压的第一电阻对（R1，R2），将第二电阻对（R3，R4）强制为负载的电压 以及耦合在第一和第二电阻对的连接点之间的有源器件（OTA，INV）。 有源器件是操作跨导放大器（OTA）或者优选地是反相器（INV）。 由于共模开环传输特性中非极性极数的减少，该调节电路为宽共模环路带宽提供共模环路稳定性。

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