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    "> Masking of switching noise in controlling a
    1.
    发明公开
    Masking of switching noise in controlling a "H" bridge 失效
    Schallrauschmaskierung im Steuerung eines“H”-Brücke

    公开(公告)号：EP0744823A1

    公开(公告)日：1996-11-27

    申请号：EP95830218.4

    申请日：1995-05-23

    申请人： SGS-THOMSON MICROELECTRONICS S.r.l.

    发明人： Fucili, Giona ,  Nessi, Maurizio

    IPC分类号： H02P7/00

    CPC分类号： H02P7/04

    摘要： Masking of switching noise is implemented in the driving system of an "H" bridge stage by exploiting the periodic signal generated by a PWM control circuit (normally present in the control system for controlling the "H" bridge in an open-loop mode) for masking the decay time of the disturbances caused by the switching from off-to-on of a first pair of switches of the bridge that drive a current in a certain direction through the load. This is implemented by keeping high for a preset period of time the periodic signal generated by the PWM circuit and varying the duty-cycle of the signal for regulating the mask time in function of the load characteristics. The system further comprises the masking of the decay interval of the disturbances caused by the switching from on-to-off of the first pair of switches and from off-to-on of the other pair of switches that provide a current ricirculation path of the energy stored in the reactance of the load, for a preset number of clock cycles, thus impeding any subsequent switching for the duration of this second mask. This second mask may be realised in different ways. The use of an up-counter and a programmable comparator been preferred.

    摘要翻译： 通过利用由PWM控制电路产生的周期性信号（通常存在于用于控制开环模式中的“H”桥）的控制系统中），在“H”桥级的驱动系统中实现开关噪声的掩蔽，用于 掩蔽由桥接器的第一对开关的断开切换引起的干扰的衰减时间，该电桥在一定方向上驱动电流通过负载。 这通过在PWM电路产生的周期性信号的预设时间段内保持高电平并且根据负载特性改变用于调节掩模时间的信号的占空比来实现。 该系统还包括屏蔽由第一对开关的开关断开引起的干扰的衰减间隔，以及提供另一对开关的另一对开关的断开间隔 存储在负载的电抗中的能量达预设数量的时钟周期，从而阻止在该第二掩模的持续时间内的任何后续切换。 该第二掩模可以以不同的方式实现。 使用递增计数器和可编程比较器是优选的。

    Output stage especially for integrated amplifiers with externally connected output power devices
    4.
    发明公开
    Output stage especially for integrated amplifiers with externally connected output power devices 失效
    输出级，特别是用于与外部连接的输出设备集成放大器。

    公开(公告)号：EP0669709A1

    公开(公告)日：1995-08-30

    申请号：EP94830090.0

    申请日：1994-02-28

    申请人： SGS-THOMSON MICROELECTRONICS S.r.l.

    发明人： Chrappan, Francesco ,  Nessi, Maurizio ,  Salina, Alberto

    IPC分类号： H03F1/32 ,  H03F3/30

    CPC分类号： H03F3/3062 ,  H02P25/034 ,  H03F1/3217 ,  H03F3/3037 ,  H03F2203/30057 ,  H03F2203/30096 ,  H03F2203/30129

    摘要： The operation of externally connected output power transistors of a class AB amplifier is controlled without employing any external sensing resistance of the output current by driving an externally connected power transistor through a level shifting buffer and employing a limiting network composed of an integrated transistor driven by the output of a signal amplifying stage and a resistance connected in series with its drain. The buffer stage shifts the level of the driving signal of the external power transistor by a value equal to the threshold voltage of the integrated transistor of the limiting network thus ensuring the turn-off of the external power transistor under quiescent conditions.

    摘要翻译： AB类放大器的外部连接的输出功率晶体管的手术，而不通过驱动通过一个水平外部连接的功率晶体管移缓冲器和使用由所述驱动的集成晶体管构成的限制网络用人的输出电流的任何外部传感电阻控制 信号放大级的输出和连接在其漏极串联的电阻。 缓冲级将这个外部功率晶体管的驱动信号的通过等于所述限制网络从而保证了外部功率晶体管的静止条件下的关断的集成晶体管的阈值电压的值的电平。

    Reduction of the transition delay of an output power transistor
    5.
    发明公开
    Reduction of the transition delay of an output power transistor 失效
    Verringerung derÜbergangszeiteines Ausgangsleistungstransistors。

    公开(公告)号：EP0627818A1

    公开(公告)日：1994-12-07

    申请号：EP93830246.0

    申请日：1993-05-31

    申请人： SGS-THOMSON MICROELECTRONICS s.r.l.

    发明人： Nessi, Maurizio

    IPC分类号： H03K17/16 ,  H03K17/04

    CPC分类号： H03K17/04213 ,  H03K17/166

    摘要： A fast-discharge switch (M1) is controlled by a comparator (M2) sensing the voltage difference between the output node and the input node of a driving integrator stage that controls the slew-rate of a power switching output transistor (MP). The fast-discharge switch turns off automatically when the output power transistor reaches (in the case of a MOS transistor) or exits (in the case of a bipolar transistor) saturation. The circuit of the invention accelerates the discharge thus reducing the turn-off delay and is insensitive of load conditions and does not affect the performance of the integrating (driver) stage that control the slew-rate.

    摘要翻译： 快速放电开关（M1）由感测输出节点和控制功率开关输出晶体管（MP）的转换速率的驱动积分器级的输入节点之间的电压差的比较器（M2）控制。 当输出功率晶体管达到（在MOS晶体管的情况下）或退出（在双极晶体管的情况下）饱和时，快速放电开关自动关闭。 本发明的电路加速了放电，从而降低了关断延迟，并且对负载条件不敏感，并且不影响控制转换速率的积分（驱动器）级的性能。

    Half-bridge turn-off slew-rate controller using a single capacitor
    6.
    发明公开
    Half-bridge turn-off slew-rate controller using a single capacitor 失效
    AbschaltbarerHalbbrücken-Austragszeit-Regler unter Verwendung eines einzelnen Kondensators。

    公开(公告)号：EP0627810A1

    公开(公告)日：1994-12-07

    申请号：EP93830247.8

    申请日：1993-05-31

    申请人： SGS-THOMSON MICROELECTRONICS S.r.l.

    发明人： Nessi, Maurizio ,  Fucili, Giona

    IPC分类号： H02P6/02

    CPC分类号： H02P6/085

    摘要： In a half-bridge output stage employing a complementary pair of output power transistors, each driven through an integrating stage for controlling the slew-rate, a single integration capacitance is conveniently shared by the two integrating stages that drive the power transistors. A pair of switches connect the single integrating capacitance to the input of either one of the two integrating stages and are controlled by a pair of nonoverlapping signals that have a certain advance with respect to the pair of logic signals that drive the half-bridge stage. In the case of a driving system of a multi-phase machine, the two configuring switches of the single integration capacitor may be driven by a pair of control signals that drive a different phase winding of the multi-phase machine, thus eliminating the need of a dedicated circuitry for generating said pair of anticipated signals to control the configuration switches.

    摘要翻译： 在采用互补输出功率晶体管对的半桥输出级中，每个驱动通过用于控制转换速率的积分级，由驱动功率晶体管的两个积分级方便地共享一个积分电容。 一对开关将单个积分电容连接到两个积分级中的任一个的输入端，并且由相对于驱动半桥级的一对逻辑信号具有一定前进的一对非重叠信号控制。 在多相机的驱动系统的情况下，单一积分电容器的两个配置开关可以由驱动多相机的不同相绕组的一对控制信号驱动，因此不需要 用于产生所述一对预期信号以控制配置开关的专用电路。

    Programmable time-interval generator
    7.
    发明公开
    Programmable time-interval generator 失效
    程序员发电机zur Erzeugung von Zeitintervallen。

    公开(公告)号：EP0618677A1

    公开(公告)日：1994-10-05

    申请号：EP93830131.4

    申请日：1993-03-31

    申请人： SGS-THOMSON MICROELECTRONICS S.r.l.

    发明人： Fucili, Giona ,  Nessi, Maurizio

    IPC分类号： H03K5/13

    CPC分类号： H03K5/13 ,  G06F1/025 ,  G06F7/62

    摘要： A programmable time-intervals generator comprising first and second digital counters, a memory, a digital divider and a digital adder. On the occurrence of a first event, the first counter starts counting, and on the occurrence of a second event, only the most significant bits of the number counted up to then are stored, thereby providing a division by truncation.
    From the stored number, at least two discrete fractions are obtained by the divider, whereafter said fractions are summed at the adder which operates on strings of bits.
    The second counter counts down the sum number and, on becoming cleared, generates a signal.

    摘要翻译： 一种可编程时间间隔发生器，包括第一和第二数字计数器，存储器，数字除法器和数字加法器。 在发生第一事件时，第一计数器开始计数，并且在发生第二事件时，仅存储直到此之后的数量的最高有效位，从而通过截断进行除法。 从存储的数字中，通过分频器获得至少两个离散分数，之后所述分数在加法器处相加，该加法器对位串进行操作。 第二个计数器对和号进行计数，并在清零时产生一个信号。