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公开(公告)号：EP0875936A2
公开(公告)日：1998-11-04
申请号：EP98303441.4
申请日：1998-05-01
发明人： Horiuchi, Michio, c/o Shinko Electric Ind. Co. Ltd , Takeuchi, Yukiharu, Shinko Electric Ind. Co. Ltd
IPC分类号： H01L23/498 , H01L21/48
CPC分类号： H01L23/49827 , H01L21/486 , H01L23/13 , H01L23/15 , H01L24/45 , H01L24/48 , H01L2224/16225 , H01L2224/16235 , H01L2224/32188 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2924/01012 , H01L2924/0102 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/12042 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/181 , H05K1/0287 , Y10S428/901 , Y10T428/24917 , Y10T428/24926 , H01L2924/00014 , H01L2924/00 , H01L2924/2076 , H01L2924/00015 , H01L2924/00012
摘要： A wiring substrate is provided in which a common core member is used and the cost can be reduced. Diameters of the penetrating filled vias (18) are the same and not more than 300 µm, and the penetrating filled vias (18) are formed on a core substrate (20) into a matrix-shape at regular intervals of not more than 2 mm. On the surface of the core substrate (20), a plane wiring pattern (17) is formed through an insulating layer (16). Each pad portion on the wiring pattern (17) is electrically connected with each corresponding via of the filled vias (18) by one to one through a connecting via (28) which penetrates the insulating layer (16), and some of the filled vias (18) are not connected with the wiring pattern (17).
摘要翻译： 提供一种布线基板，其中使用公共芯部件并且可以降低成本。 穿透填充过孔（18）的直径相同且不大于300μm，并且穿透填充的通孔（18）以不大于2的规则间隔在芯基板（20）上形成为矩阵形状 毫米。 在芯基板（20）的表面上，通过绝缘层（16）形成平面布线图案（17）。 布线图案（17）上的每个焊盘部分通过穿过绝缘层（16）的连接通孔（28）与填充过孔（18）的每个对应的通孔电连接一个一个，并且一些填充的通孔 （18）不与布线图案17连接。
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公开(公告)号：EP1018762A2
公开(公告)日：2000-07-12
申请号：EP99308086.0
申请日：1999-10-13
发明人： Kirloskar, Mohan, c/o Shinko Electric America, Inc , Horiuchi, Michio, c/o Shinko Electric Ind. Co. Ltd , Takeuchi, Yukiharu, c/o Shinko Elec. Ind. Co. Ltd.
CPC分类号： H01L23/3114 , H01L21/4846 , H01L23/49861 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device is provided which improves reliability by preventing connection defects with extensions and interface peeling occurring between a substrate and a sealing resin, and which can reduce the production cost by simplifying the fabrication process. In this semiconductor device, each lead (16) for electrically connecting an electrode terminal (12) of a semiconductor chip (10) to an external connection terminal (14) comprises an extension (17) extending parallel to an electrode terminal formation surface of the semiconductor chip (10) with a predetermined distance from the electrode terminal formation surface. An external connection terminal post (22) is provided at one of the end portions of the extension (17), and an electrode terminal post (24) is connected to the electrode terminal (12) of the semiconductor chip (10). The electrode terminal post (22) and the extension (17) are sealed by a sealing resin (18), and the distal end portion of the external connection terminal post (24) is exposed from the sealing resin (18).
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公开(公告)号：EP0875936A3
公开(公告)日：1999-05-26
申请号：EP98303441.4
申请日：1998-05-01
发明人： Horiuchi, Michio, c/o Shinko Electric Ind. Co. Ltd , Takeuchi, Yukiharu, Shinko Electric Ind. Co. Ltd
IPC分类号： H01L23/498 , H01L21/48
CPC分类号： H01L23/49827 , H01L21/486 , H01L23/13 , H01L23/15 , H01L24/45 , H01L24/48 , H01L2224/16225 , H01L2224/16235 , H01L2224/32188 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2924/01012 , H01L2924/0102 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/12042 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/181 , H05K1/0287 , Y10S428/901 , Y10T428/24917 , Y10T428/24926 , H01L2924/00014 , H01L2924/00 , H01L2924/2076 , H01L2924/00015 , H01L2924/00012
摘要： A wiring substrate is provided in which a common core member is used and the cost can be reduced. Diameters of the penetrating filled vias (18) are the same and not more than 300 µm, and the penetrating filled vias (18) are formed on a core substrate (20) into a matrix-shape at regular intervals of not more than 2 mm. On the surface of the core substrate (20), a plane wiring pattern (17) is formed through an insulating layer (16). Each pad portion on the wiring pattern (17) is electrically connected with each corresponding via of the filled vias (18) by one to one through a connecting via (28) which penetrates the insulating layer (16), and some of the filled vias (18) are not connected with the wiring pattern (17).
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