公开(公告)号：EP4439650A1

公开(公告)日：2024-10-02

申请号：EP23212798.5

申请日：2023-11-28

申请人： INTEL Corporation

发明人： MISHRA, Pratyush ,  WALL, Marcel ,  KANDANUR, Sashi ,  TADAYON, Pooya ,  PIETAMBARAM, Srinivas ,  DUONG, Benjamin ,  NAD, Suddhasattwa

IPC分类号： H01L23/15 ,  H01L23/498 ,  H01L23/522 ,  H01L23/64 ,  H01L23/66

CPC分类号： H01L23/15 ,  H01L23/49827 ,  H01L23/645 ,  H01L23/66 ,  H01L23/5227 ,  H01L23/49822

摘要： Glass-integrated inductors in integrated circuit (IC) packages are disclosed. A disclosed IC package includes a glass layer having an aperture extending therethrough, and an inductor in the aperture, the inductor including a metal core extending through the aperture, the metal core electrically coupled to interconnects on opposite sides of the glass layer, and at least one of a ferrite or a magnetic alloy in the aperture and laterally surrounding the metal core.

公开(公告)号：EP4432343A1

公开(公告)日：2024-09-18

申请号：EP23205697.8

申请日：2023-10-25

申请人： Intel Corporation

发明人： KANDANUR, Sashi ,  PIETAMBARAM, Srinivas ,  GRUJICIC, Darko ,  MARIN, Brandon ,  NAD, Suddhasattwa ,  DUONG, Benjamin ,  DUAN, Gang ,  RAHMAN, Mohammad ,  AHMED, Numair

IPC分类号： H01L23/15 ,  H01L23/498

CPC分类号： H01L23/15 ,  H01L23/49827 ,  H01L21/486 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/49833

摘要： Embodiments herein relate to systems, apparatuses, techniques and/or processes for creating a substrate out of a plurality of layers of glass, where the substrate includes one or more vias that extend through each of the plurality of layers of glass. In embodiments, a high aspect ratio via may be constructed through the substrate by electrically coupling the individual vias. Other embodiments may be described and/or claimed.

公开(公告)号：EP4421056A1

公开(公告)日：2024-08-28

申请号：EP23158217.2

申请日：2023-02-23

申请人： Heraeus Electronics GmbH & Co. KG

发明人： STEGMANN, Tamira ,  THOMAS, Sven

IPC分类号： C04B37/02 ,  C23C16/02 ,  C23F1/12 ,  H01L21/00

CPC分类号： C04B37/021 ,  C23F1/12 ,  B23K1/0016 ,  C23C14/18 ,  B23K1/008 ,  B23K1/19 ,  B23K2101/4020180801 ,  B23K2103/1220180801 ,  B23K2103/1820180801 ,  B23K2103/5220180801 ,  H01L23/3735 ,  H01L24/83 ,  H01L24/32 ,  H01L23/15 ,  C04B2237/40720130101 ,  C04B2237/0620130101

摘要： Die Erfindung betrifft ein Kupfer-Keramik-Substrat, die Verwendung eines Kupfer-Keramik-Substrats und ein Verfahren zur Herstellung einer stoffschlüssigen Verbindung zwischen einem Kupfer-Keramik-Substrat und einem Elektronikbauteil.
Das Kupfer-Keramik-Substrat umfasst a) einen Keramikkörper und b) eine Kupferschicht, die mit dem Keramikkörper flächig verbunden ist, wobei die Kupferschicht eine Oberseite aufweist. Das Kupfer-Keramik-Substrat weist vor und nach einem Sputtern der Oberseite für 120 s ein Energiespektrum, das bei einer Analyse der Oberseite der Kupferschicht durch Röntgenphotoelektronenspektroskopie erhalten wird, auf, das dem Kupfer-Keramik-Substrat eine besondere Eignung verleiht, mit einem Elektronikbauteil unter Verwendung eines Sintermaterials, das Silber umfasst, stoffschlüssig verbunden zu werden.

公开(公告)号：EP4416760A1

公开(公告)日：2024-08-21

申请号：EP22881526.2

申请日：2022-08-16

申请人： HRL Laboratories LLC

发明人： HERRAULT, Florian

IPC分类号： H01L25/065 ,  H01L23/538 ,  H01L25/00 ,  H01L23/367 ,  H01L21/683

CPC分类号： H01L25/0655 ,  H01L25/16 ,  H01L25/072 ,  H01L23/36 ,  H01L23/15 ,  H01L21/76289

公开(公告)号：EP3471517B1

公开(公告)日：2024-08-21

申请号：EP17810380.0

申请日：2017-06-08

IPC分类号： H05K1/03 ,  B23K35/30 ,  C04B37/02 ,  C22C5/06 ,  H01L23/12 ,  H05K1/02 ,  H05K3/38 ,  B23K35/00 ,  B23K35/02 ,  B23K35/26 ,  B23K35/28 ,  B23K35/32 ,  B32B15/01 ,  C22C5/08 ,  C22C9/00 ,  H01L23/15 ,  H01L23/36 ,  H01L23/498 ,  H05K3/00

CPC分类号： B23K35/30 ,  H05K1/0271 ,  H05K1/0306 ,  H05K3/0061 ,  H05K3/388 ,  H01L23/15 ,  H01L23/36 ,  H01L23/498 ,  B23K35/007 ,  B23K35/0238 ,  B32B15/018 ,  C22C5/08 ,  C04B37/026 ,  C04B2237/12620130101 ,  C04B2237/12720130101 ,  C04B2237/34320130101 ,  C04B2237/34820130101 ,  C04B2237/3620130101 ,  C04B2237/36120130101 ,  C04B2237/36320130101 ,  C04B2237/36520130101 ,  C04B2237/36620130101 ,  C04B2237/5020130101 ,  B23K35/26 ,  B23K35/286 ,  B23K35/32 ,  B23K35/325 ,  C22C9/00 ,  B23K35/3006 ,  C04B2237/12520130101 ,  C04B2237/36820130101 ,  C04B2237/40720130101 ,  C04B2237/5220130101 ,  C04B2237/6020130101 ,  C04B2237/70820130101 ,  C04B2237/7420130101

公开(公告)号：EP4362088A1

公开(公告)日：2024-05-01

申请号：EP22828807.2

申请日：2022-06-24

申请人： Amosense Co.,Ltd

发明人： BIN, Jinhyuck ,  CHO, Hyeonchoon ,  CHO, Taeho ,  YEO, Intae ,  PARK, Ikseong ,  PARK, Seunggon

IPC分类号： H01L23/498 ,  H01L23/15 ,  H01L23/48 ,  H01L23/00

CPC分类号： H01L23/498 ,  H01L23/15 ,  H01L23/48 ,  H01L23/00

摘要： The present disclosure relates to a power module comprising: a base plate; a ceramic substrate bonded to the top surface of the base plate; a semiconductor chip bonded to the top surface of the ceramic substrate; a spacer bonded to the top surface of the ceramic substrate so as to be spaced apart from the semiconductor chip; a connection pin provided at an electrode layer formed on the top surface of the spacer; and a bonding wire for connecting a terminal of the semiconductor chip to the electrode layer of the spacer.

公开(公告)号：EP3418428A1

公开(公告)日：2018-12-26

申请号：EP17753344.5

申请日：2017-02-17

申请人： Nippon Steel & Sumitomo Metal Corporation

发明人： KIMURA, Keiichi ,  TOKUHASHI, Keisuke ,  UNO, Tomohiro ,  SATO, Yutaka

IPC分类号： C23C24/04 ,  H01L23/15

CPC分类号： C23C24/04 ,  H01L23/15

摘要： A ceramic laminate improving the mechanical characteristics of a composite ceramic layer which has excellent thermal fatigue resistance, thermal conductivity, and insulation ability and having excellent durability and heat dissipation and insulation ability and a ceramic insulating substrate and a method of production of a ceramic laminate are provided.
In a cross-section perpendicular to the bonding interfaces, the average size of the second phase particles 3 is 0.02 µm to 0.3 µm and the average value of the ratio of the long axis and short axis of an equivalent ellipse when viewing a second phase particle 3 as an ellipse is 2 to 10. Further, 60% or more of the number of the second phase particles 3 has an orientation angle of 30° or less while the average orientation angle is 5° to 35°.

公开(公告)号：EP3401957A1

公开(公告)日：2018-11-14

申请号：EP17170743.3

申请日：2017-05-12

申请人： Infineon Technologies AG

发明人： Kuehle, Elmar ,  Nomann, Marianna

IPC分类号： H01L23/498

CPC分类号： H01L21/4875 ,  H01L21/481 ,  H01L23/142 ,  H01L23/15 ,  H01L23/49 ,  H01L23/49811 ,  H01L23/49833 ,  H01L24/48 ,  H01L2224/48175

摘要： A power semiconductor module arrangement comprising a base plate to be arranged in a housing, a contact element configured to, when the base plate is arranged within the housing, provide an electrical connection between the inside and the outside of the housing, and a connecting element configured to connect the contact element to the base plate. The connecting element comprises a first electrically insulating layer, a second electrically insulating layer configured to attach the contact element to the first electrically insulating layer, and a third electrically insulating layer configured to attach the first electrically insulating layer to the base plate.

公开(公告)号：EP3388877A1

公开(公告)日：2018-10-17

申请号：EP18160251.7

申请日：2018-03-06

申请人： Google LLC

发明人： LIU, Hong ,  URATA, Ryohei ,  KWON, Woon Seong ,  KANG, Teckgyu

IPC分类号： G02B6/42 ,  H05K1/18 ,  H05K1/00

CPC分类号： G02B6/428 ,  G02B6/4232 ,  G02B6/4279 ,  H01L23/147 ,  H01L23/15 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/17 ,  H01L24/81 ,  H01L25/167 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2924/1426 ,  H05K1/0274 ,  H05K1/144 ,  H05K1/181 ,  H05K1/183 ,  H05K3/3436 ,  H05K3/4688 ,  H05K2201/042 ,  H05K2201/09036 ,  H05K2201/09845 ,  H05K2201/10121 ,  H05K2201/10378 ,  H05K2201/10515 ,  H05K2201/10674 ,  H05K2201/10734 ,  H05K2201/10962 ,  Y02P70/611 ,  Y02P70/613

摘要： Signal integrity in high-speed applications is dependent on both the underlying device performance and electronic packaging methods. The maturity of chip-on-board (COB) packaging technology using wire bonding makes it a cost beneficial option for the mass production of high-speed optical transceivers. However, wire bonding introduces parasitic inductance associated with the length of the bond wires that limits the scalability of the system for higher data throughput. A high-speed optical transceiver package according to a first proposed configuration minimizes packaging related parasitic inductance by vertically integrating components using flip-chip bonding. A high-speed optical transceiver package according to a second proposed configuration minimizes packaging related parasitic inductance with horizontal tiling of components using a chip carrier and flip-chip bonding.

公开(公告)号：EP3381510A1

公开(公告)日：2018-10-03

申请号：EP18164307.3

申请日：2018-03-27

申请人： Greatbatch Ltd.

发明人： SEITZ, Keith W. ,  TANG, Xiaohong ,  THIEBOLT, William C. ,  CALAMEL, Jonathan ,  SHI, Thomas ,  MARZANO, Thomas

IPC分类号： A61N1/375

CPC分类号： A61N1/3754 ,  C03C8/14 ,  C04B2237/343 ,  C04B2237/348 ,  C04B2237/361 ,  C04B2237/363 ,  C04B2237/365 ,  C04B2237/403 ,  C04B2237/408 ,  H01L23/10 ,  H01L23/15 ,  H01L24/26 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H05K1/0306 ,  H05K3/0047 ,  H05K5/0095

摘要： Electrically conductive and hermetic vias are disposed within a flexible insulator substrate of a feedthrough assembly to provide miniaturization of feedthrough assemblies inasmuch as the feedthrough components are capable of supporting very small and hermetic conductively filled via holes in the absence of additional components, such as, for example, terminal pins, leadwires, and the like.