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公开(公告)号：EP0279605B1
公开(公告)日：1994-05-04
申请号：EP88301193.4
申请日：1988-02-12
CPC分类号： H01L29/408 , H01L29/8611
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公开(公告)号：EP0260061A3
公开(公告)日：1990-02-07
申请号：EP87307757.2
申请日：1987-09-02
IPC分类号： H01L29/78 , H01L27/08 , H03K17/687
CPC分类号： H01L27/088 , H03K17/6874 , H03K2217/0018
摘要： A transistor (30) constructed in accordance with our invention includes a substrate (31) of a first conductivity type and first and second regions (32, 33) of a second conductivity type formed within the substrate. A gate (30g1) is formed over the portion of the substrate between the first and second regions. The transistor can operate in either a first mode, in which the first region serves as a source and the second region serves as a drain, or a second mode, in which the first region serves as a drain and the second region serves as a source. During the first mode, the substrate is coupled to the first region and during the second mode, the second region is coupled to the substrate, thereby permitting the transistor to operate in forward or reverse mode, while still biasing the substrate.
摘要翻译： 根据本发明构造的晶体管（30）包括第一导电类型的衬底（31）和形成在衬底内的第二导电类型的第一和第二区域（32,33）。 在第一和第二区域之间的衬底的部分上形成栅极（30g1）。 晶体管可以在第一模式中工作，其中第一区域用作源极，第二区域用作漏极或第二模式，其中第一区域用作漏极，第二区域用作源极 。 在第一模式期间，衬底耦合到第一区域，并且在第二模式期间，第二区域耦合到衬底，从而允许晶体管以正向或反向模式工作，同时仍然偏置衬底。
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公开(公告)号：EP0227894A2
公开(公告)日：1987-07-08
申请号：EP86112729.8
申请日：1986-09-15
CPC分类号： H01L29/7802 , H01L29/1095 , H01L29/41766 , H01L29/6634
摘要： A process for manufacturing a vertical DMOS transistor minimizes the number of steps requiring alignment. The processing includes the steps of forming a polycrystalline silicon gate structure (108) on a wafer of N type silicon (102), using the gate structure to define a P region (114) and an N+ region (116) within the P region, etching through a portion of the N region to expose the underlying P region, and then forming a metal layer (124) which contacts the P region and the remaining portion of the N region. Prior to the formation of the metal contacts, the method of the present invention requires no alignment steps.
摘要翻译： 用于制造垂直DMOS晶体管的工艺使需要对准的步骤数量最小化。 该处理包括以下步骤：在N型硅（102）的水上形成多晶硅栅极结构（108），使用栅极结构来限定P区内的P区（114）和N +区（116） 蚀刻通过N区域的一部分以暴露下面的P区域，然后形成接触P区域和N区域的剩余部分的金属层（124）。 在形成金属触点之前，本发明的方法不需要对准步骤。
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4.发明公开
公开(公告)号：EP0287195A1
公开(公告)日：1988-10-19
申请号：EP88301192.6
申请日：1988-02-12
CPC分类号： H01L27/0688 , H01L29/4238 , H01L29/435
摘要： A power MOS transistor includes a polycrystalline silicon layer (18) which provides connection to act as a resistor between the first portion (26) of gate metallization disposed above the gate of the device, and a second portion (28) of gate metallization adjacent to the active source/gate region of the device.
摘要翻译： 功率MOS晶体管包括多晶硅层（18），其提供连接以用作设置在器件栅极之上的栅极金属化的第一部分（26）和邻近栅极金属化的第二部分（28）之间的电阻器 器件的有源源极/栅极区域。
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公开(公告)号：EP0279605A2
公开(公告)日：1988-08-24
申请号：EP88301193.4
申请日：1988-02-12
CPC分类号： H01L29/408 , H01L29/8611
摘要： A semiconductor device has a substrate with regions (54, 56) of first and second conductivity types forming a junction (58) extending to a surface (60) of the substrate, an oxide layer (66, 68) on the surface and covering the junction and a charged ion region in the oxide layer extending from adjacent the junction at the surface of the substrate over part of the region (54) of first conductivity type, the polarity of the ions in the ion region being that of the region of first conductivity type, whereby the breakdown voltage of the device is increased.
摘要翻译： 半导体器件具有衬底，其具有第一和第二导电类型的区域（54,56），形成延伸到衬底的表面（60）的接合部（58），表面上的氧化物层（66,68） 接头和氧化物层中的带电离子区域，其在第一导电类型的区域（54）的一部分上的从衬底的表面处的结的相邻延伸，离子区域中的离子的极性是第一 导电类型，从而提高器件的击穿电压。
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公开(公告)号：EP0225962A3
公开(公告)日：1988-01-07
申请号：EP86107569
申请日：1986-06-04
发明人： Bencuya, Izak , Cogan, Adrian I.
CPC分类号： H01L29/1095
摘要： An insulated gate transistor (70) modified to increase its latching current density. On one side of gate (22), a high conductivity collector well (76) is provided to divert current which would otherwise flow through collector well (24) in a critical path (50) along source-collector junction (27), tending to forward bias the junction and cause the transistor to latch.
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公开(公告)号：EP0225962A2
公开(公告)日：1987-06-24
申请号：EP86107569.5
申请日：1986-06-04
发明人： Bencuya, Izak , Cogan, Adrian I.
CPC分类号： H01L29/1095
摘要： An insulated gate transistor (70) modified to increase its latching current density. On one side of gate (22), a high conductivity collector well (76) is provided to divert current which would otherwise flow through collector well (24) in a critical path (50) along source-collector junction (27), tending to forward bias the junction and cause the transistor to latch.
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8.发明公开Method of fabricating a high voltage semiconductor device 失效Verfahren zur Herstellung einer Hochspannungshalbleiteranordnung。
公开(公告)号：EP0279902A2
公开(公告)日：1988-08-31
申请号：EP87114532.2
申请日：1987-10-05
发明人： Cogan, Adrian I.
CPC分类号： H01L21/761 , H01L29/41
摘要： A semiconductor device capable of handling high voltages includes a relatively thick epitaxial layer (42) the top surface of which defines a plurality of generally V-shaped grooves (50,52,54,56), a pair of the grooves (50,56) having positioned therebetwen active device regions (64, 72; 66, 74, 76; 68, 78), such pair of grooves acting as isolation regions including impurity regions (60,62) extending on both sides of the groove through the epitaxial layer to a lower layer (40). A pair of grooves (52, 54) inward of the first-mentioned grooves contact active regions of the device into which the V-shaped portions extend, again with each such V-shaped portion having impurity regions 80, 82 extending on both sides thereof. The impurity regions associated with the V-shaped grooves are formed simultaneously with other active regions of the device.
摘要翻译： 能够处理高电压的半导体器件包括相对厚的外延层（42），其外表面的顶表面限定了多个大致V形的沟槽（50,52,54,56），一对沟槽（50,56） ），其位于有源器件区域（64,72; 66,74,76; 68,78）之间，所述一对沟槽用作隔离区域，包括通过外延层在沟槽的两侧延伸的杂质区域（60,62） 到下层（40）。 首先提到的凹槽内的一对凹槽（52,54）与V形部分延伸的装置的活动区域接触，再次，每个这样的V形部分具有在其两侧延伸的杂质区域80,82 。 与V形槽相关联的杂质区域与器件的其它有源区域同时形成。
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公开(公告)号：EP0241059A3
公开(公告)日：1988-08-24
申请号：EP87200388
申请日：1987-03-03
CPC分类号： H01L29/66712 , H01L21/76897 , H01L29/0619 , H01L29/0638 , H01L29/402 , H01L29/513 , H01L29/518 , H01L29/66333 , H01L29/7811
摘要： A process for manufacturing a DMOS transistor in accordance with the present invention including the steps of forming a layer of gate insulation (12, 14) on an N type substrate (10). A layer of polycrystalline silicon (16) is formed on the gate insulation layer. A first mask is used to define the polycrystalline silicon gate. A layer of silicon dioxide (20) is then formed on the polycrystalline silicon gate. A second photolithographic mask is formed on the wafer. The second photolithographic mask defines the region where electrical contact is to be made to the polycrystalline silicon gate as well as where a deep body region (24) is to be formed in the semiconductor substrate. The deep body region is then formed. Thereafter, portions of the gate insulation layer not covered by the polycrystalline silicon gate are removed. The P type body region (26) and N+ source region (28) are then formed having a lateral extent defined by the edge of the polycrystalline silicon gate. A conductive layer 30 is formed on the wafer and photolithographically patterned, thereby leaving a gate contact and a source and body contact. A passivation layer 34 is then formed on the wafer, portions of which are photolithographically removed, thereby defining bonding pads. Of importance, the above-described process uses only four photolithographic masking steps.
摘要翻译： 根据本发明的制造DMOS晶体管的方法包括以下步骤：在N型衬底（10）上形成栅极绝缘层（12,14）。 在栅极绝缘层上形成多晶硅层（16）。 第一个掩模用于定义多晶硅栅极。 然后在多晶硅栅极上形成一层二氧化硅（20）。 在晶片上形成第二光刻掩模。 第二光刻掩模限定了要与多晶硅栅极形成电接触的区域以及在半导体衬底中要形成深体区（24）的区域。 然后形成深体区域。 此后，去除未被多晶硅栅极覆盖的栅极绝缘层的部分。 然后形成具有由多晶硅栅极的边缘限定的横向范围的P型体区域（26）和N +源极区域（28）。 导电层30形成在晶片上并且光刻图案化，从而留下栅极接触以及源和体接触。 然后在晶片上形成钝化层34，其中光刻地去除部分钝化层34，从而限定焊盘。 重要的是，上述方法仅使用四个光刻掩模步骤。
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公开(公告)号：EP0260061A2
公开(公告)日：1988-03-16
申请号：EP87307757.2
申请日：1987-09-02
IPC分类号： H01L29/78 , H01L27/08 , H03K17/687
CPC分类号： H01L27/088 , H03K17/6874 , H03K2217/0018
摘要： A transistor (30) constructed in accordance with our invention includes a substrate (31) of a first conductivity type and first and second regions (32, 33) of a second conductivity type formed within the substrate. A gate (30g1) is formed over the portion of the substrate between the first and second regions. The transistor can operate in either a first mode, in which the first region serves as a source and the second region serves as a drain, or a second mode, in which the first region serves as a drain and the second region serves as a source. During the first mode, the substrate is coupled to the first region and during the second mode, the second region is coupled to the substrate, thereby permitting the transistor to operate in forward or reverse mode, while still biasing the substrate.
摘要翻译： 根据本发明构造的晶体管（30）包括第一导电类型的衬底（31）和形成在衬底内的第二导电类型的第一和第二区域（32,33）。 在第一和第二区域之间的衬底的部分上形成栅极（30g1）。 晶体管可以在第一模式中工作，其中第一区域用作源极，第二区域用作漏极或第二模式，其中第一区域用作漏极，第二区域用作源极 。 在第一模式期间，衬底耦合到第一区域，并且在第二模式期间，第二区域耦合到衬底，从而允许晶体管以正向或反向模式工作，同时仍然偏置衬底。
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