公开(公告)号：EP0124960A3

公开(公告)日：1988-01-07

申请号：EP84300995

申请日：1984-02-16

申请人： STC PLC

发明人： Scovell, Peter Denis ,  Rosser, Paul John ,  Tomkins, Gary John

IPC分类号： H01L21/28 ,  H01L21/90

CPC分类号： H01L29/66575 ,  H01L21/28052 ,  H01L21/28105 ,  H01L21/76889 ,  H01L29/665

摘要： Polysilicon elements of integrated circuits, for example gates (24) or interconnects, are provided with metallic silicide layers (26) in order to take advantage of the lower resistivity thereof. The polysilicon elements are defined on an oxide layer (23) disposed on a silicon substrate (20) before polysilicon metallisation. After polysilicon metallisation the metal and polysilicon are caused to interdiffuse to form silicide layers (26) covering the polysilicon elements (24).

摘要翻译： 集成电路的多晶硅元件（例如栅极（24）或互连）设置有金属硅化物层（26），以便利用其较低的电阻率。 多晶硅元件限定在在多晶硅金属化之前设置在硅衬底（20）上的氧化物层（23）上。 在多晶硅金属化之后，导致金属和多晶硅相互扩散以形成覆盖多晶硅元件（24）的硅化物层（26）。

公开(公告)号：EP0202727A3

公开(公告)日：1988-03-23

申请号：EP86300865

申请日：1986-02-10

申请人： STC PLC

发明人： Scovell, Peter Denis ,  Baker, Roger Leslie ,  Blomley, Peter Fred ,  Tomkins, Gary John

IPC分类号： H01L21/00 ,  H01L21/28 ,  H01L29/08 ,  H01L29/10

CPC分类号： H01L21/0337 ,  Y10S148/01 ,  Y10S148/011 ,  Y10S148/124

摘要： A fully self-aligned polycrystalline silicon emitter bipolar transistor. Self-alignment of the p + base contact (12) is achieved by using oxidised sidewalls (8) (sidewall spacers) of the emitter mesa (7) as part of the p + base contact implantation mask. Collector contact (13) alignment can be achieved using oxidised sidewalls (17) of polycrystalline silicon alignment mesas (14) defined inthe same polysilicon asthe emitter mesa (7) but deposited on oxide (2) rather than the implanted base region (5).

公开(公告)号：EP0174773A2

公开(公告)日：1986-03-19

申请号：EP85306106.7

申请日：1985-08-29

申请人： STC PLC

发明人： Scovell, Peter Denis ,  Rosser, Paul John ,  Tomkins, Gary John

IPC分类号： H01L23/52 ,  H01L21/90

CPC分类号： H01L21/76886 ,  H01L21/76889 ,  H01L23/53257 ,  H01L2924/0002 ,  Y10S148/019 ,  H01L2924/00

摘要： 57 In order to prevent diffusion of silicon from under a titanium disilicide interconnect (1) and into an overlying aluminium layer (6), the disilicide is selectively nitrided at the points where interconnection between the disilicide and aluminium is required via holes (4) in a silicon dioxide layer (3). The titanium nitride contacts (5) thus formed in a truly self-aligned manner provide a good barrier to silicon diffusion whilst having an acceptable low resistivity.

公开(公告)号：EP0174773B1

公开(公告)日：1991-02-06

申请号：EP85306106.7

申请日：1985-08-29

申请人： STC PLC

发明人： Scovell, Peter Denis ,  Rosser, Paul John ,  Tomkins, Gary John

IPC分类号： H01L23/52 ,  H01L21/90

CPC分类号： H01L21/76886 ,  H01L21/76889 ,  H01L23/53257 ,  H01L2924/0002 ,  Y10S148/019 ,  H01L2924/00

公开(公告)号：EP0124960A2

公开(公告)日：1984-11-14

申请号：EP84300995.2

申请日：1984-02-16

申请人： STC PLC

发明人： Scovell, Peter Denis ,  Rosser, Paul John ,  Tomkins, Gary John

IPC分类号： H01L21/28 ,  H01L21/90

CPC分类号： H01L29/66575 ,  H01L21/28052 ,  H01L21/28105 ,  H01L21/76889 ,  H01L29/665

摘要： Polysilicon elements of integrated circuits, for example gates (24) or interconnects, are provided with metallic silicide layers (26) in order to take advantage of the lower resistivity thereof. The polysilicon elements are defined on an oxide layer (23) disposed on a silicon substrate (20) before polysilicon metallisation. After polysilicon metallisation the metal and polysilicon are caused to interdiffuse to form silicide layers (26) covering the polysilicon elements (24).

摘要翻译： 集成电路的多晶硅元件（例如栅极（24）或互连）设置有金属硅化物层（26），以便利用其较低的电阻率。 多晶硅元件限定在在多晶硅金属化之前设置在硅衬底（20）上的氧化物层（23）上。 在多晶硅金属化之后，导致金属和多晶硅相互扩散以形成覆盖多晶硅元件（24）的硅化物层（26）。