公开(公告)号：EP4390935A1

公开(公告)日：2024-06-26

申请号：EP23216192.7

申请日：2023-12-13

Applicant: STMicroelectronics S.r.l.

Inventor： ZURLA, Riccardo ,  PASOTTI, Marco ,  CARISSIMI, Marcella ,  CABRINI, Alessandro

IPC: G11C13/00 ,  G11C11/54 ,  G11C7/10 ,  G06N3/063

CPC classification number: G06N3/063 ,  G11C7/1006 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/007120130101 ,  G11C13/0004 ,  G11C13/0026 ,  G11C2013/004520130101 ,  G11C11/54 ,  G11C13/0028 ,  G06N3/065

Abstract: An in-memory computation device (10) receives an input signal (X) indicative of a plurality of input values (x1,...,xN) and provides an output signal (y1,...,yM). The in-memory computation device has: a word line activation unit (14) that receives the input signal and provides activation signals (21), each as a function of an input value; a memory array (12) and a digital detector (22). The memory array has a plurality of memory cells (20) coupled to a bit line (BLi) and each to a word line (WLj). The memory cells store each a computational weight (gij), receive each an activation signal (21), and are flown through each by a cell current (icell) that is a function of the activation signal and the computational weight. The bit line is flown through by a bit line current (IBL,i) that is a summation of the cell currents. The digital detector is coupled to the bit line, has an integration stage (33) and a counter stage (34) and performs successive iterations. In each iteration: the integration stage generates an integration signal indicative of a time integral of the bit line current, compares the integration signal with a threshold, and resets the integration signal in response to the integration signal reaching the threshold; and the counter stage updates the output signal in response to the integration signal reaching the threshold.

公开(公告)号：EP4216017A1

公开(公告)日：2023-07-26

申请号：EP23151962.0

申请日：2023-01-17

Applicant: STMicroelectronics S.r.l.

Inventor： PASOTTI, Marco ,  CAPECCHI, Laura ,  ZURLA, Riccardo ,  CARISSIMI, Marcella

IPC: G05F1/575

Abstract: A voltage regulator receives a reference voltage and generates a regulated voltage using a MOSFET having a gate terminal configured to receive a control voltage. A charge pump receives the regulated voltage and generates a charge pump voltage in response to an enable signal and a clock signal generated in response to the enable signal. The voltage regulator further includes a first switched capacitor circuit coupled to the gate terminal and configured to selectively charge a first capacitor with a first current and impose a first voltage drop on the control voltage in response to assertion of the enable signal. The voltage regulator also includes a second switched capacitor circuit coupled to the gate terminal and configured to selectively charge a second capacitor with a second current and impose a second voltage drop on the control voltage in response to one logic state of the clock signal.

公开(公告)号：EP4390934A1

公开(公告)日：2024-06-26

申请号：EP23215491.4

申请日：2023-12-11

Applicant: STMicroelectronics S.r.l.

Inventor： CARISSIMI, Marcella ,  PASOTTI, Marco ,  ZURLA, Riccardo

IPC: G11C13/00 ,  G11C11/54 ,  G11C7/10 ,  G11C7/12 ,  G06N3/065 ,  G11C5/14

CPC classification number: G11C13/0004 ,  G11C11/54 ,  G11C13/004 ,  G11C13/0026 ,  G11C2013/004520130101 ,  G11C7/1006 ,  G11C7/12 ,  G11C13/0028 ,  G11C13/0061 ,  G06N3/065 ,  G11C5/147

Abstract: An in-memory computation device (10) receives an input signal (X) indicative of a plurality of input values (x1, ... ,xN) and provides an output signal (y1, ... , yM). The in-memory computation device has: a word line activation unit (14) that receives the input signal and provides activation signals (21), each as a function of an input value; a memory array (12), a biasing circuit (18) and a digital detector (22) . The biasing circuit provides a bias voltage starting from a reference current. The memory array has a plurality of memory cells (20) coupled to a bit line (BLi) and each to a word line (WLj). The memory cells store each a computational weight (gij), receive each an activation signal (21), and are flown through each by a cell current (icell) that is a function of the bias voltage, the activation signal and the computational weight. The bit line is flown through by a bit line current (IBL,i) that is a summation of the cell currents. The digital detector is coupled to the bit line, samples the bit line current and, in response, provides the output signal.

公开(公告)号：EP3648108A1

公开(公告)日：2020-05-06

申请号：EP19206356.8

申请日：2019-10-30

Applicant: STMicroelectronics S.r.l.

Inventor： PASOTTI, Marco ,  ZURLA, Riccardo ,  CABRINI, Alessandro ,  TORELLI, Guido ,  VOLPE, Flavio Giovanni

IPC: G11C13/00 ,  G11C7/14

Abstract: A phase-change memory device (1), comprising: a memory array (2) of PCM cells, a variable current generator (4), and a sense amplifier (6). The current generator (4) comprises a reference array (4a) of PCM cells programmed in SET resistance state. The phase-change memory device further comprises a decoder for addressing each cell of the reference array so that a respective plurality of SET current signals is generated through the plurality of reference cells; and a controller (12) configured to receive at input said SET current signals, select a number of SET current signals having the lowest current values among the plurality of SET current signals, calculate a mean value of said lowest current values, and adjust the reference current (i ref ) to be lower than said mean value.

公开(公告)号：EP3772061A1

公开(公告)日：2021-02-03

申请号：EP20188675.1

申请日：2020-07-30

Applicant: STMicroelectronics S.r.l.

Inventor： CAPECCHI, Laura ,  PASOTTI, Marco ,  CARISSIMI, Marcella ,  ZURLA, Riccardo

IPC: G11C5/14 ,  G11C8/08 ,  G11C13/00 ,  G11C7/14

Abstract: Current-generator circuit (100) for supplying a resistive load (102) through a driver (110, 128), comprising a compensation circuit (112) including a resistive block (120) having an electrical resistance (R load ') which is a function of the resistance of the resistive load (102). The resistive block (120) mimics the resistance seen by the driver during the supplying operation. The driver is driven in such a way to generate a compensated current pulse (I CTR ) which balances non-idealities and channel-modulation effects introduced by the resistance of the load during the supplying operation.