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    Thin film semiconductor memory and manufacture method therefor
    1.
    发明公开
    Thin film semiconductor memory and manufacture method therefor 有权
    Dünnschicht-Halbleiterspeicher und Verfahren zu seiner Herstellung

    公开(公告)号：EP1355358A2

    公开(公告)日：2003-10-22

    申请号：EP03252253.4

    申请日：2003-04-09

    申请人： Seiko Instruments Inc. ,  Hayashi, Yutaka

    发明人： Hayashi, Yutaka ,  Hasegawa, Hisashi, c/o Seiko Instruments Inc. ,  Yoshida, Yoshifumi, c/o Seiko Instruments Inc. ,  Osanai, Jun, c/o Seiko Instruments Inc.

    IPC分类号： H01L27/108

    CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/10802 ,  H01L27/10844 ,  Y10S257/908

    摘要： A memory cell which is formed on a fully depleted SOI or other semiconductor thin film and which operates at low voltage without needing a conventional large capacitor is provided as well as a memory cell array. The semiconductor thin film is sandwiched between first and second semiconductor regions which face each other across the semiconductor thin film and which have a first conductivity type. A third semiconductor region having the opposite conductivity type is provided in an extended portion of the semiconductor thin film. From the third semiconductor region, carriers of the opposite conductivity type are supplied to and accumulated in the semiconductor thin film portion to change the gate threshold voltage of a first conductivity type channel that is induced by a first conductive gate voltage in the semiconductor thin film between the first and second semiconductor regions through an insulating film.

    摘要翻译： 提供了形成在完全耗尽的SOI或其他半导体薄膜上并且在低电压下工作而不需要常规的大电容器的存储单元，以及存储单元阵列。 半导体薄膜（100）夹在半导体薄膜之间彼此相对并且具有第一导电类型的第一（110）和第二（120）半导体区域之间。 具有相反导电类型的第三半导体区域（130）设置在半导体薄膜的延伸部分中。 从第三半导体区域，将相反导电类型的载流子提供给并累积在半导体薄膜部分中，以改变由半导体中的第一导电栅极（310）电压引起的第一导电类型沟道的栅极阈值电压 通过绝缘膜（210）在第一和第二半导体区域之间的薄膜。

    Insulated gate thin film transistor and control system therefor
    3.
    发明公开
    Insulated gate thin film transistor and control system therefor 有权
    SteuermethodefürDünnfilmtransistormit isoliertem Gate

    公开(公告)号：EP1353386A2

    公开(公告)日：2003-10-15

    申请号：EP03252252.6

    申请日：2003-04-09

    申请人： Seiko Instruments Inc. ,  Hayashi, Yutaka

    发明人： Hayashi, Yutaka ,  Hasegawa, Hisashi, c/o Seiko Instruments Inc. ,  Yoshida, Yoshifumi, c/o Seiko Instruments Inc. ,  Osanai, Jun, c/o Seiko Instruments Inc.

    IPC分类号： H01L29/786 ,  H01L21/336

    CPC分类号： H01L29/78615 ,  H01L21/84 ,  H01L27/1203

    摘要： The gate threshold voltage is electronically controlled in an insulated gate transistor formed in a semiconductor thin film, such as fully depleted SOI, that is depleted of carriers between first and second principal surfaces. A third semiconductor region of the opposite conductivity type is placed such that it is in contact with the semiconductor thin film. The amount of carriers in the semiconductor thin film is controlled by supplying the semiconductor thin film with carriers of the opposite conductivity type from the third semiconductor region, or by drawing carriers of the opposite conductivity type from the semiconductor thin film into the third semiconductor region.

    摘要翻译： 栅极阈值电压在形成在半导体薄膜（例如完全耗尽的SOI）中的绝缘栅晶体管中被电子控制，其在第一和第二主表面之间耗尽载流子。 相反导电型的第三半导体区域被放置成使其与半导体薄膜接触。 半导体薄膜中的载流子的量通过向半导体薄膜提供与第三半导体区域相反的导电类型的载流子，或通过将相反导电类型的载流子从半导体薄膜拉入第三半导体区域来控制。

    Semiconductor device including protection means and manufacturing method thereof
    5.
    发明公开
    Semiconductor device including protection means and manufacturing method thereof 失效
    Halbleiterbauelement mit einem Schutzmittel und Herstellungsverfahren。

    公开(公告)号：EP0675543A2

    公开(公告)日：1995-10-04

    申请号：EP95302171.4

    申请日：1995-03-31

    申请人： SEIKO INSTRUMENTS INC.

    发明人： Saitoh, Yutaka, c/o Seiko Instruments Inc. ,  Osanai, Jun, c/o Seiko Instruments Inc.

    IPC分类号： H01L27/02

    CPC分类号： H01L27/027 ,  H01L27/0251 ,  H01L27/0277 ,  H01L29/861

    摘要： An improvement of a resistance to electrostatic discharge of a semiconductor integrated circuit device is provided. An IC having a high ESD immunity is realised by causing a surface concentration of N type impurities in a drain area (409) of an N-channel type MOS transistor to be more than 5 E 18/cm 3 and in the direction of a source area (401) to have a monotonously decreasing concentration profile in which there is no kink in a portion less than 5 E 18/cm 3 in the surface region under a gate electrode (410).

    摘要翻译： 提供了半导体集成电路器件的抗静电放电性的改进。 通过使N沟道型MOS晶体管的漏极区域（409）中的N型杂质的表面浓度大于5E 18 / cm 3，并且在 源区域（401）>具有单调减小的浓度分布，其中在栅电极（410）下的表面区域中部分小于5E 18 / cm 3的部分没有扭结。

    Insulated gate semiconductor device and method for fabricating the same
    6.
    发明公开
    Insulated gate semiconductor device and method for fabricating the same 失效
    Halbleiterbauelement mit isoliertem门和dessen Herstellungsverfahren。

    公开(公告)号：EP0673069A3

    公开(公告)日：1996-07-31

    申请号：EP95301892.6

    申请日：1995-03-20

    申请人： SEIKO INSTRUMENTS INC.

    发明人： Yoshida, Yoshifumi, c/o Seiko Instruments Inc. ,  Yoshida, Shinichi, c/o Seiko Instruments Inc. ,  Saitoh, Yutaka, c/o Seiko Instruments Inc. ,  Osanai, Jun, c/o Seiko Instruments Inc.

    IPC分类号： H01L27/06 ,  H01L21/8238 ,  H01L21/3205 ,  H01L27/092

    CPC分类号： H01L21/823842 ,  H01L27/0925

    摘要： A semiconductor device and a fabrication is provided, which reduces the fabrication cost and effectively lowers the operating voltage. In a process for fabricating the semiconductor device comprising high-resistance polysilicon and a polysilicon gate CMOS transistor, introduction of ions into polysilicon gates uses ion implantation of forming source and drain regions. By using the above constitution, 2 masks and 30 processes are saved. Moreover, because both channels become the surface channel type, the operating voltage can be lowered. The minimum operating voltage of the voltage detector fabricated by the fabrication method of the present invention shows approx. 0.25 V at room temperature and 0.35 V or less even at -40°C.

    摘要翻译： 提供一种半导体器件和制造方法，其是为了降低制造成本并有效降低工作电压。 在用于制造包括高电阻多晶硅和多晶硅栅极CMOS晶体管的半导体器件的工艺中，将离子引入多晶硅栅极使用形成源极和漏极区域的离子注入。 通过使用上述结构，可以节省2个掩模和30个处理。 此外，由于两个通道都成为表面通道型，所以可以降低工作电压。 通过本发明的制造方法制造的电压检测器的最小工作电压， 在室温下为0.25V，即使在-40℃也为0.35V以下

    Insulated gate semiconductor device and method for fabricating the same
    8.
    发明公开
    Insulated gate semiconductor device and method for fabricating the same 失效
    Herstellungsverfahrenfürein Halbleiterbauelement mit isoliertem Gate

    公开(公告)号：EP0673069A2

    公开(公告)日：1995-09-20

    申请号：EP95301892.6

    申请日：1995-03-20

    申请人： SEIKO INSTRUMENTS INC.

    发明人： Yoshida, Yoshifumi, c/o Seiko Instruments Inc. ,  Yoshida, Shinichi, c/o Seiko Instruments Inc. ,  Saitoh, Yutaka, c/o Seiko Instruments Inc. ,  Osanai, Jun, c/o Seiko Instruments Inc.

    IPC分类号： H01L27/06 ,  H01L21/8238 ,  H01L21/3205 ,  H01L27/092

    CPC分类号： H01L21/823842 ,  H01L27/0925

    摘要： A semiconductor device and a fabrication is provided, which reduces the fabrication cost and effectively lowers the operating voltage. In a process for fabricating the semiconductor device comprising high-resistance polysilicon and a polysilicon gate CMOS transistor, introduction of ions into polysilicon gates uses ion implantation of forming source and drain regions. By using the above constitution, 2 masks and 30 processes are saved. Moreover, because both channels become the surface channel type, the operating voltage can be lowered. The minimum operating voltage of the voltage detector fabricated by the fabrication method of the present invention shows approx. 0.25 V at room temperature and 0.35 V or less even at -40°C.

    摘要翻译： 提供一种半导体器件和制造方法，其是为了降低制造成本并有效降低工作电压。 在用于制造包括高电阻多晶硅和多晶硅栅极CMOS晶体管的半导体器件的工艺中，将离子引入多晶硅栅极使用形成源极和漏极区域的离子注入。 通过使用上述结构，可以节省2个掩模和30个处理。 此外，由于两个通道都成为表面通道型，所以可以降低工作电压。 通过本发明的制造方法制造的电压检测器的最小工作电压， 在室温下为0.25V，即使在-40℃也为0.35V以下