公开(公告)号：EP1632845A3

公开(公告)日：2008-01-23

申请号：EP05255138.9

申请日：2005-08-19

申请人： SUN MICROSYSTEMS, INC.

发明人： Chaudhry, Shailender ,  Caprioli, Paul ,  Tremblay, Marc

IPC分类号： G06F9/30 ,  G11C7/10

CPC分类号： G06F9/30141 ,  G06F9/383 ,  G06F9/3867 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/1075 ,  G11C8/08 ,  G11C2207/107 ,  G11C2207/108

摘要： One embodiment of the present invention provides a processor that supports multiple-issue execution. This processor includes a register file, which contains an array of memory cells, wherein the memory cells contain bits for architectural registers of the processor. The register file also includes multiple read ports and multiple write ports to support multiple-issue execution. During operation, if multiple read ports simultaneously read from a given register, the register file is configured to: read each bit of the given register out of the array of memory cells through a single bitline associated with the bit; and to use a driver located outside of the array of memory cells to drive the bit to the multiple read ports. In this way, each memory cell only has to drive a single bitline (instead of multiple bitlines) during a multiple-port read operation, thereby allowing memory cells to use smaller and more power-efficient drivers for read operations.

公开(公告)号：EP1369786A3

公开(公告)日：2005-03-23

申请号：EP03252741.8

申请日：2003-04-30

申请人： Sun Microsystems, Inc.

发明人： Tremblay, Marc ,  Chaudhry, Shailender ,  Jacobson, Quinn A.

IPC分类号： G06F11/10 ,  G06F11/14 ,  G06F9/38

CPC分类号： G06F11/1032 ,  G06F9/3836 ,  G06F9/3857 ,  G06F9/3861 ,  G06F11/1405

摘要： One embodiment of the present invention provides a system that corrects bit errors in temporary results within a central processing unit (CPU). During operation, the system receives a temporary result during execution of an in-flight instruction. Next, the system generates a parity bit for the temporary result, and stores the temporary result and the parity bit in a temporary register within the CPU. Before the temporary result is committed to the architectural state of the CPU, the system checks the temporary result and the parity bit to detect a bit error. If a bit error is detected, the system performs a micro-trap operation to re-execute the instruction that generated the temporary result, thereby regenerating the temporary result. Otherwise, if a bit error is not detected, the system commits the temporary result to the architectural state of the CPU.

公开(公告)号：EP1369786B1

公开(公告)日：2006-12-13

申请号：EP03252741.8

申请日：2003-04-30

申请人： SUN MICROSYSTEMS, INC.

发明人： Tremblay, Marc ,  Chaudhry, Shailender ,  Jacobson, Quinn A.

IPC分类号： G06F11/10 ,  G06F11/14 ,  G06F9/38

CPC分类号： G06F11/1032 ,  G06F9/3836 ,  G06F9/3857 ,  G06F9/3861 ,  G06F11/1405

公开(公告)号：EP1632845A2

公开(公告)日：2006-03-08

申请号：EP05255138.9

申请日：2005-08-19

申请人： SUN MICROSYSTEMS, INC.

发明人： Chaudhry, Shailender ,  Caprioli, Paul ,  Tremblay, Marc

IPC分类号： G06F9/30

CPC分类号： G06F9/30141 ,  G06F9/383 ,  G06F9/3867 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/1075 ,  G11C8/08 ,  G11C2207/107 ,  G11C2207/108

摘要： One embodiment of the present invention provides a processor that supports multiple-issue execution. This processor includes a register file, which contains an array of memory cells, wherein the memory cells contain bits for architectural registers of the processor. The register file also includes multiple read ports and multiple write ports to support multiple-issue execution. During operation, if multiple read ports simultaneously read from a given register, the register file is configured to: read each bit of the given register out of the array of memory cells through a single bitline associated with the bit; and to use a driver located outside of the array of memory cells to drive the bit to the multiple read ports. In this way, each memory cell only has to drive a single bitline (instead of multiple bitlines) during a multiple-port read operation, thereby allowing memory cells to use smaller and more power-efficient drivers for read operations.

摘要翻译： 本发明的一个实施例提供一种支持多次执行的处理器。 该处理器包括一个寄存器文件，该寄存器文件包含存储单元阵列，其中存储单元包含处理器结构寄存器的位。 注册文件还包括多个读取端口和多个写入端口，以支持多次执行。 在操作期间，如果从给定寄存器同时读取多个读取端口，则寄存器文件被配置为：通过与该位相关联的单个位线，从存储器单元阵列读出给定寄存器的每个位; 并且使用位于存储器单元阵列之外的驱动器将该位驱动到多个读取端口。 以这种方式，每个存储器单元仅在多端口读取操作期间仅驱动单个位线（而不是多个位线），从而允许存储器单元使用较小且更省电的驱动器进行读取操作。

公开(公告)号：EP1369786A2

公开(公告)日：2003-12-10

申请号：EP03252741.8

申请日：2003-04-30

申请人： Sun Microsystems, Inc.

发明人： Tremblay, Marc ,  Chaudhry, Shailender ,  Jacobson, Quinn A.

IPC分类号： G06F11/10

CPC分类号： G06F11/1032 ,  G06F9/3836 ,  G06F9/3857 ,  G06F9/3861 ,  G06F11/1405

摘要： One embodiment of the present invention provides a system that corrects bit errors in temporary results within a central processing unit (CPU). During operation, the system receives a temporary result during execution of an in-flight instruction. Next, the system generates a parity bit for the temporary result, and stores the temporary result and the parity bit in a temporary register within the CPU. Before the temporary result is committed to the architectural state of the CPU, the system checks the temporary result and the parity bit to detect a bit error. If a bit error is detected, the system performs a micro-trap operation to re-execute the instruction that generated the temporary result, thereby regenerating the temporary result. Otherwise, if a bit error is not detected, the system commits the temporary result to the architectural state of the CPU.

摘要翻译： 本发明的一个实施例提供的系统中的中央处理单元（CPU）内的确在临时结果校正的位错误。 在手术过程中，该系统的飞行指令的执行期间接收临时结果。 接着，系统基因我们获得了临时结果的奇偶校验位，并存储临时结果和在CPU内的临时寄存器的奇偶校验位。 临时结果致力于CPU的架构状态之前，系统会检查临时结果和校验位来检测的位错误。 如果检测到比特错误，系统将执行的微陷阱手术重新执行该指令并生成的临时结果，从而再生临时结果。 否则，如果没有检测到比特错误，系统将提交临时结果到CPU的结构状态。