A modified radiant heat source with isolated optical zones
    2.
    发明公开
    A modified radiant heat source with isolated optical zones 失效
    EinegeänderteHeizstrahlungsquelle mit isolierten optischen Zonen。

    公开(公告)号:EP0641016A1

    公开(公告)日:1995-03-01

    申请号:EP94104495.0

    申请日:1994-03-22

    IPC分类号: H01L21/00

    CPC分类号: H01L21/67115

    摘要: A thin reflective cylindrical baffle [20] in a radiant lamp heater is provided in the space below a plurality of heating bulbs [2,4,6] (arranged in a center position and around a middle and outer ring) and above a quartz window [12]. The baffle diameter is such that it fits within the annular space between the middle [4] and outer [6] ring of bulbs. The baffle [20] allows improved controllability of wafer temperature profile -for a wafer heated by a radiant lamp heater.

    摘要翻译: 晶片加热器包括在多个加热灯泡(2,4,6)之间的空间中的薄反射圆柱形挡板(20),位于中间和外圈之间的中心位置以及石英窗(12)之上, 。 挡板直径使其适合在两个同心圆环之间的环形空间内。 挡板阻挡由灯产生的预设量的光。 挡板与灯泡环同心。 灯泡可以安装在组件中,部分涂覆有光反射材料,例如, 金或铬,在组件中有冷却剂通道。 县。 挡板包括冷却剂通道,连接管用于冷却剂流动。 挡板材料可以是石英,不锈钢,钼或组合。

    High pressure photoresist silylating process and apparatus
    4.
    发明公开
    High pressure photoresist silylating process and apparatus 失效
    Hochdruck-Photolack Siliconisierungsverfahren und Vorrichtung。

    公开(公告)号:EP0359221A2

    公开(公告)日:1990-03-21

    申请号:EP89116936.9

    申请日:1989-09-13

    IPC分类号: G03F7/38 H01L21/00

    CPC分类号: G03F7/265

    摘要: Disclosed herein are a method and apparatus for silylation of positive or negative photosensitive resist layer on a semiconductor wafer after the resist layer has been exposed to radiant energy through a mask which includes introducing a silylating agent to the wafer at high pressure over 760 torr and, usually, at temperatures less than 180° C. Increased pressure increases the rate of silylation, allows practical use of lower process temperatures, and, therefore, allows better process control. The apparatus for applying the high pressure silylation process includes a process chamber having a port and a process gas inlet; a heated substrate in the process chamber; a loadlock in fluid communication with the process chamber through the port; and a gas generator in fluid communication with the process chamber through the gas inlet.

    摘要翻译: 本文公开了一种在抗蚀剂层已经通过掩模暴露于辐射能之后在半导体晶片上使正或负光敏抗蚀剂层甲硅烷基化的方法和装置,其包括在高于760托的高压下将硅烷化剂引入晶片, 通常,在低于180℃的温度下,增加的压力提高了甲硅烷基化速率,允许实际使用较低的工艺温度,因此允许更好的过程控制。 用于施加高压甲硅烷化方法的装置包括具有端口和工艺气体入口的处理室; 处理室中的加热衬底; 通过端口与处理室流体连通的负载锁; 以及通过气体入口与处理室流体连通的气体发生器。

    Processing apparatus and method
    5.
    发明公开
    Processing apparatus and method 失效
    处理装置和方法

    公开(公告)号:EP0303030A1

    公开(公告)日:1989-02-15

    申请号:EP88110013.5

    申请日:1988-06-23

    IPC分类号: C23C16/50 C23C16/54

    CPC分类号: C23C16/54 C23C16/517

    摘要: A processing apparatus (1300) and method wherein an integrated circuit wafer (48) is exposed to activated species generated by a first plasma (1326) which is separate from the wafer (48), but is in the process gas flow stream (1322) upstream of the wafer, and is also exposed to ion bombardment generated by a second plasma which has a dark space which substantially adjoins the surface (54) of the wafer (48). It is useful to keep the in situ plasma at a relatively low-power, so that the remote plasma can gener­ate activated species, and therefore the in situ plasma power level can be adjusted to optimize the ion bombardment energy.

    摘要翻译: 一种处理装置(1300)和方法,其中集成电路晶片(48)暴露于由与晶片(48)分离但处于工艺气流(1322)中的第一等离子体(1326)产生的活化物种, 在晶片的上游,并且还暴露于由第二等离子体产生的离子轰击,该第二等离子体具有基本上邻接晶片(48)的表面(54)的暗区。 将原位等离子体保持在相对较低的功率是有用的,以便远程等离子体可以产生活化物质,并且因此可以调整原位等离子体功率水平以优化离子轰击能量。

    Processing apparatus and method
    6.
    发明公开
    Processing apparatus and method 失效
    处理装置和方法

    公开(公告)号:EP0299248A1

    公开(公告)日:1989-01-18

    申请号:EP88110011.9

    申请日:1988-06-23

    IPC分类号: H01L21/31 C23C16/50

    CPC分类号: H01L21/31 C23C16/517

    摘要: A process for photoresist ashing which utilizes the combination of remote (1326) and in situ plasma (1312, 1314) in a low pressure process module (1300) and the plasma is generated form a mixture of Oxygen and one of a group of CF₄, CHF₃, H₂, H₂O, HCl, HBr, Cl₂, and N₂O with the process chamber within the process module being generally at ambient temperatures.

    摘要翻译: 在低压处理模块(1300)中利用远程(1326)和原位等离子体(1312,1314)的组合来产生光致抗蚀剂灰化的过程,并且等离子体由氧气和一组CF 4中的一个的混合物产生, CHF 3,H 2,H 2 O,HCl,HBr,Cl 2和N 2 O,处理模块内的处理室通常处于环境温度。

    Plasma processing method and apparatus
    7.
    发明公开
    Plasma processing method and apparatus 失效
    Verfahren undGerätzur Plasmabehandlung。

    公开(公告)号:EP0210605A2

    公开(公告)日:1987-02-04

    申请号:EP86110241.6

    申请日:1986-07-25

    IPC分类号: H01J37/32

    CPC分类号: H01J37/32431

    摘要: A plasma reactor apparatus and method wherein one electrode 10 of the plasma reactor, which is not the electrode 14 to which the integrated circuit wafer being processed is attached, consists essentially of monocrystalline material, preferably silicon. Preferably this is a single slice reactor. Preferably the silicon electrode 10 has holes drilled through it for gas flow.

    摘要翻译: 等离子体反应器装置和方法,其中不是正在处理的集成电路晶片的电极14的等离子体反应器的一个电极10基本上由单晶材料,优选硅组成。 优选地,这是单片反应器。 优选地,硅电极10具有穿过其的钻孔用于气流。

    Automated single slice powered load lock plasma reactor
    8.
    发明公开
    Automated single slice powered load lock plasma reactor 失效
    用于步骤合步骤与自动输入闸室工作的等离子体反应器。

    公开(公告)号:EP0180373A2

    公开(公告)日:1986-05-07

    申请号:EP85307443.3

    申请日:1985-10-16

    CPC分类号: H01J37/32

    摘要: A plasma reactor 28 for the manufacturing of semiconductor devices has powered loadlocks and a main process chamber where slices can be processed one slice at a time with pre-etch plasma treatments before the main etching processing and afterwards receive a post etch treatment. The system comprises powered loadlocks 21, 59 a main chamber, 37, vacuum pumps 29A and 29B, 31, radio frequency power supplier 51, radio frequency matching networks 53A, 53B, 53C, heat exchangers 63 and throttle valve 45 and pressure controllers, gas flow distribution 43 an microprocessor controllers 25 and 27. The semiconductor wafers are automatically fed one at a time from storage cassettes through isolation gates with articulated mechanical arms 145 to a powered entry loadlock 21 for pre-etching processes. At the completion of the pre-etching processing, the semiconductor wafer is transferred to the main chamber 37 automatically for the main etch process and then to the powered exit loadlock 45 for post etch treatment and finally to an output cassette.