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    METHOD AND ARRANGEMENT IN A PACKET SWITCH FOR CONGESTION AVOIDANCE USING A COMMON QUEUE AND SEVERAL SWITCH STATES
    2.
    发明公开
    METHOD AND ARRANGEMENT IN A PACKET SWITCH FOR CONGESTION AVOIDANCE USING A COMMON QUEUE AND SEVERAL SWITCH STATES 审中-公开
    方法和系统，分组交换卡纸避免使用通用等待提案和多VERMITTLUNGSZUSTûNDE

    公开(公告)号：EP1554843A1

    公开(公告)日：2005-07-20

    申请号：EP03751689.5

    申请日：2003-10-10

    申请人： Telefonaktiebolaget LM Ericsson (publ)

    发明人： HANSSON, Ulf ,  ERNKELL, Mats ,  PETERSEN, Lars-Göran

    IPC分类号： H04L12/56 ,  H04Q11/04

    CPC分类号： H04L47/29 ,  H04L47/10 ,  H04L47/12 ,  H04L47/266 ,  H04L47/30 ,  H04L49/101 ,  H04L49/3045

    摘要： A packet switching network has switches and sending/receiving entities interconnected by links (L6) utilized as paths between different users. A switch has an ingress part (I1) with a buffer including virtual queues (VQl, VQ2, VQ3). These are connected to the link (L6) and to a switch core. The queues have threshold detectors (TH1, TH2, TH3) and are connected to states (STA - STD). When the queue (VQ1) is congested by packets the path occupying the individually greatest part of the queue is noted. If noted for the first time the path is stored in a free one of the states (STA,1,2) and corresponding sending entity is halted (XOFF). If the same path is noted again on repeated congestion a bandwidth value (3) is counted up. A chronological order for the states (STA-STD) is established. When all states (STA-STD) are occupied an older half of the states is selected, the path with the lowest count value is further selected, its state is purged and the corresponding sending entity is released (XON).

    ESTABLISHING TELECOMMUNICATION CONNECTIONS
    3.
    发明授权
    ESTABLISHING TELECOMMUNICATION CONNECTIONS 失效
    生产电讯联系

    公开(公告)号：EP0966860B1

    公开(公告)日：2006-05-31

    申请号：EP98909900.7

    申请日：1998-03-02

    申请人： TELEFONAKTIEBOLAGET LM ERICSSON (publ)

    发明人： OLSSON, Fredrik ,  LINDBERG, Mikael ,  HANSSON, Ulf

    IPC分类号： H04Q11/06

    CPC分类号： H04Q11/06 ,  H04Q2213/13208 ,  H04Q2213/13392

    摘要： The invention relates to a method and device for switching user data, belonging to a connection, between different time slots in a switch or a switch stage such that sequence and frame integrity are preserved. According to the invention, an efficient algorithm is utilized for determining distribution information, in form of storage positions in one or more control memories in the switch. User data is caused to be switched, according to this distribution information from the algorithm, such that these user data maintain the same reciprocal time order through the switch or switch stage. The distribution information determined by the algorithm assures sequence integrity and at the same time minimizes the delay of user data through the switch and/or switch stage. The algorithm also generates control information in form of delay values for delaying some user data such that data belonging to incoming time slots in one and the same frame are assigned to outgoing time slots in the same frame.

    MOBILE TERMINAL SLEEP PHASE ASSIGNMENT AND ANNOUNCEMENT IN A WIRELESS LOCAL AREA NETWORK
    5.
    发明授权
    MOBILE TERMINAL SLEEP PHASE ASSIGNMENT AND ANNOUNCEMENT IN A WIRELESS LOCAL AREA NETWORK 有权
    ZUWEISUNG UND ANSAGE DER SCHLAFPHASE A EINMOBILENDGERÄTIN EINEM DRATHLOSEN LOKALEN NETZ

    公开(公告)号：EP1169818B1

    公开(公告)日：2011-05-04

    申请号：EP00921260.6

    申请日：2000-03-28

    申请人： Telefonaktiebolaget LM Ericsson (publ)

    发明人： LINDSKOG, Jan ,  ALMEHAG, Lorens ,  EBENHARD, Johan ,  MALMGREN, Göran ,  WENGER, Fabian ,  HANSSON, Ulf

    IPC分类号： H04W52/02

    CPC分类号： H04L29/06 ,  H04L69/324 ,  H04W52/0229 ,  Y02D70/142

    摘要： In a WLAN where an AP and MTs use a duplex airlink having a MAC frame structure to communicate with each other, the AP places wakeup PDUs at different locations in a MAC frame to allow the MTs to conserve energy by maximizing sleep time. In other embodiments, the wakeup PDUs are sequenced by MAC-ID so that a MT can conclusively determine whether remaining wakeup PDUs in a sequence can contain its MAC-ID, and go to sleep early if they cannot. In another embodiment, a wakeup PDU type can indicate to a corresponding MT whether the MT can expect downlink data later in the same MAC frame. In addition, the wakeup PDU type can indicate to the MT that the MAC frame that it should awaken and remain awake to receive downlink data in the future.

    摘要翻译： 在AP和MT使用具有MAC帧结构的双工空中链路相互通信的WLAN中，AP在MAC帧中的不同位置放置唤醒PDU，以允许MT通过最大化睡眠时间来节省能量。 在其他实施例中，唤醒PDU通过MAC-ID进行排序，使得MT可以最终确定序列中的剩余唤醒PDU是否可以包含其MAC-ID，并且如果它们不能早早睡觉。 在另一个实施例中，唤醒PDU类型可以向相应的MT指示MT是否可以在同一MAC帧中稍后期望下行链路数据。 此外，唤醒PDU类型可以向MT指示其应该唤醒并保持唤醒的MAC帧以在将来接收下行链路数据。

    DEVICE AND METHOD IN A SEMICONDUCTOR CIRCUIT
    7.
    发明授权
    DEVICE AND METHOD IN A SEMICONDUCTOR CIRCUIT 有权
    设备和方法的半导体电路

    公开(公告)号：EP1350323B1

    公开(公告)日：2007-06-27

    申请号：EP00986120.4

    申请日：2000-12-05

    申请人： TELEFONAKTIEBOLAGET LM ERICSSON (publ)

    发明人： LINDBERG, Mikael ,  DAVIDSSON, Stefan ,  HANSSON, Ulf

    IPC分类号： H03L7/00 ,  H03K5/22

    CPC分类号： H04L7/0037 ,  H03K5/133 ,  H03K5/135 ,  H03L7/07 ,  H03L7/0814 ,  H04J3/0688

    摘要： The figure shows a unit (5) for distributing clock signals (SA1, SB1) in telecommunication systems. The unit is provided with a semi-conductor arrangement (ADA, CTA, RDA) for generating a predetermined time delay. Two clocks (CLA, CLB) are connected to two parallel, redundant semi-conductor circuits (SCA, SCB) emitting clock signals (SA2, SB2) from multiplexers (MXA, MXB). These receive delayed clock signals (SA1) from one of the clocks (CLA), and from the other clock (CLB) clock signals (SB1) that are delayed in adjustable delay circuits (ADA, ADB) to be phased in with the clock signals (SA1) from the first clock. Thus, a number of delay elements in the delay circuit (ADA) are connected and a first reference number of delay elements, providing a predetermined delay time, are connected in a reference delay circuit (RDA). A quotient of the two numbers is stored. One of the semi-conductor circuits (SCA) is replaced by an alternative semi-conductor circuit (SCA1), the reference delay circuit (RDA1) of which is set on the predetermined delay time, corresponding to a second reference number of delay elements. An adjustable delay circuit (ADA1) is set on the same delay time as the replaced semi-conductor circuit (SCA, ADA), by means of the second reference number and the quotient. The adjustable delay circuit (ADA, ADA1) and the reference delay circuit (RDA, RDA1) on the same semi-conductor circuit (SCA, SCA1) must be produced in a common process to enable all the delay elements to have identical time delays.

    REDUNDANCY TERMINATION FOR DYNAMIC FAULT ISOLATION
    8.
    发明授权
    REDUNDANCY TERMINATION FOR DYNAMIC FAULT ISOLATION 有权
    于动态故障隔离REDONDANTER报表

    公开(公告)号：EP1036483B1

    公开(公告)日：2006-08-30

    申请号：EP98962781.5

    申请日：1998-12-07

    申请人： TELEFONAKTIEBOLAGET LM ERICSSON (publ)

    发明人： LINDBERG, Mikael ,  HANSSON, Ulf ,  PETTERSSON, Johan

    IPC分类号： H04Q11/04 ,  H04L12/56 ,  G06F11/10

    CPC分类号： H04Q11/04 ,  H04Q2213/1305 ,  H04Q2213/13162 ,  H04Q2213/13166 ,  H04Q2213/13167 ,  H04Q2213/13292 ,  H04Q2213/13305 ,  H04Q2213/1332 ,  H04Q2213/1334

    摘要： The invention relates to a fault tolerant processing system comprising at least two processing planes. Each processing plane processes an input signal and generates an output signal. The system further comprises plane termination logic for receiving the output signals of the processing planes to generate a non-redundant output signal. According to the invention, each processing plane is provided with means for detecting a fault in the plane, and means for substituting, in response to detection of a fault in the plane, a signal component, referred to as control component, representing a predetermined logical state for each one of those components of the processed input signal that are affected by the detected fault. Furthermore, the plane termination logic comprises means for performing logical operations on the output signals of the planes such that, in the generation of the non-redundant output signal, unaffected signal components of a received signal override corresponding control components of another received signal.

    TIME SWITCH STAGES AND SWITCHES
    9.
    发明授权
    TIME SWITCH STAGES AND SWITCHES 失效
    TIME教育水平和调停要素

    公开(公告)号：EP0966861B1

    公开(公告)日：2005-12-14

    申请号：EP98909901.5

    申请日：1998-03-02

    申请人： TELEFONAKTIEBOLAGET LM ERICSSON (publ)

    发明人： OLSSON, Fredrik ,  LINDBERG, Mikael ,  HANSSON, Ulf

    IPC分类号： H04Q11/06

    CPC分类号： H04Q11/06 ,  H04Q2213/13056 ,  H04Q2213/13103 ,  H04Q2213/13208 ,  H04Q2213/13213 ,  H04Q2213/1331

    摘要： The invention relates to the preservation of sequence integrity (TSSI) and frame integrity (TSFI) in switching wideband connections through a switch or a switch stage. The speech memory (17) in a switch stage (6.n) in the switch is extended to include storage positions (44.n) that in number correspond to the number of time slots in two frames. These storage positions are arranged into two parts (48, 49) of the same size in the speech memory (17). Furthermore, there is provided a delay control unit (26) in the time switch stage (6.n) for generating delay information based on control information in the control memory (23) of the switch stage (6.n) and a determined part of the counter information from a time slot counter circuit (28). This delay information controls, for each time slot, to/from (depending on if the speech memory (17) is arranged in an outgoing stage or an incoming stage) which one of the first (48) and second part (49) of the speech memory (17) that user data is switched.