公开(公告)号：EP3208984A4

公开(公告)日：2017-10-11

申请号：EP15850547

申请日：2015-10-15

申请人： WILKERSON BENJAMIN P

发明人： WILKERSON BENJAMIN P

IPC分类号： H04L27/233 ,  H03H7/18 ,  H03H7/30 ,  H03H11/04 ,  H03H17/00 ,  H03K3/023 ,  H03K5/1252 ,  H03K19/003 ,  H03K19/20 ,  H04B1/7163 ,  H04L7/033 ,  H04W4/00 ,  H04W84/18

CPC分类号： H04L27/233 ,  H03K5/2481 ,  H03K19/01728 ,  H03K19/01855 ,  H03K19/0963 ,  H04L7/0278 ,  H04L27/2331 ,  H04L27/2334 ,  H04L27/2335 ,  H04W4/008

摘要： An embodiment of the present invention relates to a low-power broadband asynchronous BPSK demodulation method and a configuration of a circuit thereof. In connection with a configuration of a BPSK demodulation circuit, there may be provided a low-power wideband asynchronous binary phase shift keying demodulation circuit comprising: a sideband separation and lower sideband signal delay unit for separating a modulated signal into an upper sideband and a lower sideband using a primary high pass filter, which has a carrier frequency as the cutoff frequency thereof, and a primary low pass filter and digitalizing the same into a positive phase and a negative phase such that, in connection with a digital output from a lower sideband comparator and a digital output from an upper sideband comparator, signals with opposite phases are compared at the same ascending edge and at the same descending edge between a symbol edge and another symbol edge, respectively, thereby reducing jitter to the largest extent, improving the yield ratio, and outputting lower sideband digital signals and upper sideband digital signals, the lower sideband digital signals having been delayed by the 1/4 frequency of the carrier frequency; a data demodulation unit for generating a first symbol edge signal detected by aligning the phase difference between a delayed lower sideband positive-phase digital signal and an upper sideband negative-phase digital signal to be 180° and generating a second symbol edge signal detected by aligning the phase difference between a delayed lower sideband negative-phase digital signal and an upper sideband positive-phase digital signal to be 180°, the data demodulation unit overlapping the first symbol edge signal and the second symbol edge signal through an AND gate, thereby reducing the glitch and generating a symbol edge clock, which has no glitch, through a deglitch filter, the data demodulation unit synchronizing the delayed lower sideband positive-phase digital signal with a descending edge of the symbol edge signal, thereby demodulating data; and a data clock restoration unit for generating a data clock using the delayed lower sideband positive-phase digital signal and the demodulated data signal.

公开(公告)号：EP3214811A4

公开(公告)日：2018-06-13

申请号：EP15855860

申请日：2015-10-29

申请人： WILKERSON BENJAMIN P

发明人： WILKERSON BENJAMIN P

IPC分类号： H04L27/233

CPC分类号： H04L27/233 ,  H04L27/2331 ,  H04L27/2334

摘要： A BPSK demodulator circuit comprises: a sideband-separating and lower sideband signal-delaying unit which separates a modulated signal into a lower sideband and an upper sideband by a primary low pass filter and a primary high pass filter having a cut-off frequency as a carrier frequency, and which outputs an upper sideband analog signal and an analog signal delayed by 1/4 of a cycle of the carrier frequency from a lower sideband analog signal; a data demodulating unit which demodulates digital data by means of, since the phase difference of the delayed lower sideband analog signal and the upper sideband analog signal is aligned at 180 degrees, latching, through a hysteresis circuit, an analog pulse signal appearing in accordance with the phase change part of a signal, that is, a BPSK modulation signal, generated by the sum of the analog signals; and a data clock restoring unit which generates a data clock by using a data signal and a signal having the delayed lower sideband analog signal digitized through a comparator.

公开(公告)号：EP3188428A4

公开(公告)日：2017-09-06

申请号：EP15836598

申请日：2015-08-24

申请人： WILKERSON BENJAMIN P

发明人： WILKERSON BENJAMIN P

IPC分类号： H04L27/233 ,  H03H7/18 ,  H03H7/30 ,  H03H11/04 ,  H03K3/023 ,  H03K3/3565 ,  H04B1/7163 ,  H04L7/033 ,  H04L27/00 ,  H04W4/00 ,  H04W84/18

CPC分类号： H04L27/2331 ,  H04B1/71637 ,  H04B2201/71636 ,  H04L7/0278 ,  H04L27/0014 ,  H04L27/2334 ,  H04L27/2335 ,  H04L2027/0036 ,  H04W4/008

摘要： An embodiment of the present invention relates to an ultra low power wideband asynchronous binary phase shift keying (BPSK) demodulation method and a circuit configuration thereof. Provided is an ultra low power wideband asynchronous BPSK demodulation circuit configured by comprising: a sideband division and upper sideband signal delay unit dividing a modulated signal into an upper sideband and a lower sideband by a first order high-pass filter and a first order low-pass filter of which a cutoff frequency is a carrier frequency, so as to output an analog signal delayed by a ¼ period of the carrier frequency from an upper sideband analog signal, and a lower sideband analog signal; a data demodulation unit latching, through a hysteresis circuit, a signal generated by a difference between the analog signals in which a phase difference between the delayed upper sideband analog signal and the lower sideband analog signal is aligned at 0°, that is, an analog pulse signal indicated according to a phase shift part of a BPSK modulation signal, so as to demodulate digital data; and a data clock recovery unit for generating a data clock by using a signal digitalized from the lower sideband analog signal through a comparator and a data signal.

摘要翻译： 本发明的一个实施例涉及超低功率宽带异步二进制相移键控（BPSK）解调方法及其电路配置。 提供一种超低功率宽带异步BPSK解调电路，包括：边带分割和上边带信号延迟单元，通过一阶高通滤波器和一阶低通滤波器将调制信号分成上边带和下边带， 其截止频率为载波频率，以从上边带模拟信号和下边带模拟信号输出延迟了载波频率的1/4周期的模拟信号; 数据解调单元通过迟滞电路锁存由延迟的上边带模拟信号和下边带模拟信号之间的相位差在0°排列的模拟信号之间的差异所产生的信号，即，模拟信号 根据BPSK调制信号的相移部分指示脉冲信号，以解调数字数据; 以及数据时钟恢复单元，用于通过使用通过比较器和数据信号从下边带模拟信号数字化的信号来生成数据时钟。