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    PROGRAMMABLE IC WITH SAFETY SUB-SYSTEM
    8.
    发明公开
    PROGRAMMABLE IC WITH SAFETY SUB-SYSTEM 审中-公开
    具有安全子系统的可编程IC

    公开(公告)号：EP3198725A1

    公开(公告)日：2017-08-02

    申请号：EP15767633.9

    申请日：2015-09-04

    申请人： Xilinx, Inc.

    发明人： AHMAD, Sagheer ,  TAYLOR, Bradley, L. ,  ARBEL, Ygal

    IPC分类号： H03K19/003 ,  G06F15/78 ,  H03K19/177 ,  H03K19/007

    CPC分类号： H03K19/003 ,  G06F15/7867 ,  H03K19/007 ,  H03K19/177 ,  H03K19/17764 ,  H03K19/17768

    摘要： A programmable IC is disclosed that includes a programmable logic sub-system, a processing sub-system, and a safety sub-system. The programmable logic sub-system includes programmable logic circuits configured to form a hardware portion of a user design. The processing sub-system includes processing circuits configured to execute a software portion of a user design. The safety sub-system is configured to perform a safety functions that detect and/or mitigate errors in circuits of the programmable IC. The safety sub-system includes hard-wired circuits configured to perform hardware-based safety functions for a first subset of circuits of the programmable IC. The safety sub-system also includes a processing circuit configured to execute software-based safety functions for a second subset of circuits of the programmable IC.

    摘要翻译： 公开了一种可编程IC，其包括可编程逻辑子系统，处理子系统和安全子系统。 可编程逻辑子系统包括配置成形成用户设计的硬件部分的可编程逻辑电路。 处理子系统包括被配置为执行用户设计的软件部分的处理电路。 安全子系统被配置为执行检测和/或减轻可编程IC的电路中的错误的安全功能。 安全子系统包括配置成为可编程IC的第一电路子集执行基于硬件的安全功能的硬连线电路。 安全子系统还包括处理电路，其被配置为执行用于可编程IC的电路的第二子集的基于软件的安全功能。

    DOMAIN ASSIST PROCESSOR-PEER FOR COHERENT ACCELERATION
    9.
    发明公开
    DOMAIN ASSIST PROCESSOR-PEER FOR COHERENT ACCELERATION 审中-实审

    公开(公告)号：EP4414856A2

    公开(公告)日：2024-08-14

    申请号：EP24184773.0

    申请日：2020-04-08

    申请人： Xilinx, Inc.

    发明人： DASTIDAR, Jaideep ,  AHMAD, Sagheer

    IPC分类号： G06F15/78

    CPC分类号： G06F15/7889

    摘要： Examples herein describe a peripheral I/O device with a domain assist processor (DAP) and a domain specific accelerator (DSA) that are in the same coherent domain as CPUs and memory in a host computing system. Peripheral I/O devices were previously unable to participate in a cache-coherent shared-memory multiprocessor paradigm with hardware resources in the host computing system. As a result, domain assist processing for lightweight processor functions (e.g., open source functions such as gzip, open source crypto libraries, open source network switches, etc.) either are performed using CPUs resources in the host or by provisioning a special processing system in the peripheral I/O device (e.g., using programmable logic in a FPGA). The embodiments herein use a DAP in the peripheral I/O device to perform the lightweight processor functions that would otherwise be performed by hardware resources in the host or by a special processing system in the peripheral I/O device.