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公开(公告)号：EP1206087B1
公开(公告)日：2007-01-24
申请号：EP01309620.1
申请日：2001-11-14
发明人： Tzeng, Shrjie
CPC分类号： H04L49/351 , H04L12/5601 , H04L47/10 , H04L47/15 , H04L47/266 , H04L47/50 , H04L47/522 , H04L47/623 , H04L49/205 , H04L49/206 , H04L49/3009 , H04L49/354 , H04L49/606 , H04L49/90 , H04L49/901 , H04L2012/5621
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2.发明授权
公开(公告)号：EP1195955B1
公开(公告)日：2006-12-20
申请号：EP01308394.4
申请日：2001-10-02
CPC分类号： H04L12/4633 , H04J3/062 , H04L47/29 , H04L47/30 , H04L47/32 , H04L49/103 , H04L49/205 , H04L49/254 , H04L49/351 , H04L2012/5665 , H04L2012/5681 , H04L2012/5682
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公开(公告)号：EP1227628B1
公开(公告)日：2005-09-28
申请号：EP02100081.5
申请日：2002-01-30
IPC分类号： H04L12/56
CPC分类号： H04L47/10 , H04L49/351 , H04L49/503
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4.发明公开Method and apparatus of sharing an inter-chip bus for message passing and memory access 有权用于分发芯片间总线用于消息传输和存储器访问的方法和装置
公开(公告)号：EP1199642A3
公开(公告)日：2003-10-29
申请号：EP01308430.6
申请日：2001-10-02
发明人： Fan, Jason , Sokol, Michael
CPC分类号： H04L12/4633 , G06F13/4022 , H04J3/062 , H04L47/29 , H04L47/30 , H04L47/32 , H04L49/103 , H04L49/205 , H04L49/254 , H04L49/351 , H04L2012/5665 , H04L2012/5681 , H04L2012/5682
摘要： A system of switches having a memory/command bus having a first interface, a second interface and a third interface. A memory is connected to the third interface of the memory/command bus. The memory has a first memory address. A first switch monitors the memory/command bus and interprets information written to the first memory address as proxy information. The first switch is connected to the first interface of the memory/command bus. The second switch monitors the memory/command bus and interprets information written to the first memory address as proxy information. The second switch is connected to the second interface of the memory/command bus.
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公开(公告)号：EP1248415A3
公开(公告)日：2003-10-01
申请号：EP01308479.3
申请日：2001-10-03
IPC分类号： H04L12/56
CPC分类号： H04L49/45 , H04L49/103 , H04L49/351 , H04L49/352
摘要： A network of switches having a first switch having a first memory interface and a first expansion port. The network also has an expansion bus having a first expansion bus interface and a second expansion bus interface. The first expansion bus interface is connected to the first expansion port. A second switch has a second memory interface and a second expansion port. The second expansion port is connected to the second expansion bus interface, thereby connecting the first switch to the second switch, wherein the expansion bus allows the first switch to directly access the second memory interface through the second switch and the second switch to directly access the first memory interface through the first switch.
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6.发明公开System and method of improving memory yield in frame buffer memory using failing memory location 有权电路和方法，用于使用缺陷存储器位置改善帧缓冲存储器的利用程度
公开(公告)号：EP1324349A2
公开(公告)日：2003-07-02
申请号：EP02028177.0
申请日：2002-12-19
发明人： Tzeng, Shrjie
IPC分类号： G11C29/00
CPC分类号： G11C29/883 , G11C29/44 , G11C29/78 , G11C29/88 , G11C2029/1208
摘要： A method is provided for testing buffer memory. The method includes a step of testing a buffer memory having a plurality of memory locations including redundant memory locations, to determine if any of the plurality of memory locations are unusable. Next, an address of an unusable memory location of the plurality of memory locations is determined. Next, the address of the unusable memory location is stored. Next, a use of the unusable memory location is prevented based on the stored address of the unusable memory location.
摘要翻译： 提供了一种用于测试缓冲存储器的方法。 该方法包括：测试具有的存储器位置，包括冗余存储器位置的多个缓冲存储器，以确定矿如果任何的存储器位置的多个不可用的步骤。 接着，为了解决存储器位置的多个不可用的存储器位置的确定性被开采。 接下来，将不可用的存储器位置的地址被存储。 接着，使用不可用的存储器位置是基于不可用的存储器位置的所存储的地址阻止。
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7.发明授权Using shadow Mcast/Bcast/Dlf counter and free pointer counter to balance unicast and Mcast/Bcast/Dlf frame ratio 有权使用影子MCAST / BCAST / DLF计数器和自由指针计数器，用于平衡的单播和MCAST / BCAST / DLF帧比
公开(公告)号：EP1361709B1
公开(公告)日：2010-12-29
申请号：EP03010378.2
申请日：2003-05-08
发明人： Tzeng, Shrjie
IPC分类号： H04L12/56
CPC分类号： H04L49/901 , H04L47/10 , H04L47/15 , H04L47/266 , H04L47/29 , H04L47/32 , H04L49/201 , H04L49/351 , H04L49/352 , H04L49/90
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8.发明公开A fairness scheme method and apparatus for pause capable and pause incapable ports 审中-公开信号基于等处理方法的原理和相应的设备，用于使能中断和非无缝连接能够
公开(公告)号：EP1361710A3
公开(公告)日：2006-05-10
申请号：EP03010478.0
申请日：2003-05-09
发明人： Tzeng, Shrjie , Hao, Yi-Hsien
IPC分类号： H04L12/56
CPC分类号： H04L47/10 , H04L47/24 , H04L47/2441 , H04L47/266 , H04L47/29 , H04L47/30 , H04L47/31 , H04L47/32 , H04L49/3009 , H04L49/351
摘要： A network device, which includes a port, a tag generation unit and a flow control module, is provided. The port, which is connected to a network entity, is configured to send and receive a data packet. The tag generation unit is configured to generate a tag based upon the network entity. The tag generation unit is also configured to add the tag to the data packet and to activate the tag. The flow control module is coupled with a buffer, and is configured to control storage of the data packet into the buffer. The flow control module is also coupled with the port, and is configured to control a communication session conducted between the network device and the network entity based upon the tag.
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公开(公告)号：EP1184764B1
公开(公告)日：2005-11-09
申请号：EP01000411.7
申请日：2001-08-30
发明人： SOKOL, Michael , CHEN, Xi
IPC分类号： G05B23/02
CPC分类号： G05B19/042 , G05B2219/23154
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10.发明公开
公开(公告)号：EP1207640A3
公开(公告)日：2005-10-19
申请号：EP01308917.2
申请日：2001-10-19
发明人： Chang, Michael , Sokol, Michael
CPC分类号： G06F1/3203 , G06F1/324 , G06F5/065 , G06F2205/064 , H04J3/0697 , H04L49/103 , H04L49/205 , H04L49/254 , H04L49/351 , H04L2012/5665 , H04L2012/5681 , H04L2012/5682 , Y02D10/126
摘要： A system for reducing clock speed and power consumption in a network chip. The system has a core that transmits and receives signals at a first clock speed. A receive buffer is in communication with the core and configured to transmit the signals to the core at the first clock speed. A transmit buffer is in communication with the core and configured to receive signals from the core at the first clock speed. A sync is configured to receive signals in the receive buffer at a second clock speed and to transmit the signals from the transmit buffer at the second clock speed. The sync is in communication with the transmit buffer and the receive buffer.
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