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    LIQUID CRYSTAL MACROCYCLES
    3.
    发明公开
    LIQUID CRYSTAL MACROCYCLES 失效
    液晶大环

    公开(公告)号：EP0891388A1

    公开(公告)日：1999-01-20

    申请号：EP97907224.0

    申请日：1997-03-19

    申请人： The Secretary of State for Defence in Her Britannic Majesty's Government of The United Kingdom of Great Britain and Northern I

    发明人： MEHL, Georg, Hans, Rudolf ,  GOODBY, John, William ,  TUFFIN, Rachel, Patricia ,  TOYNE, Kenneth, Johnson

    IPC分类号： C08G77 ,  C09K19

    CPC分类号： C09K19/406 ,  C08G77/38 ,  C09K19/408

    摘要： Materials of formula (I) are provided wherein E=0 indicates a non-cyclic system, E=1 indicates a cyclic system; when E=0 then G is R3SiR1R2(O)k; R1, R2, R3 are independently selected from C1-16 alkyl which may be partly or fully halogenated, H and formula (IA) wherein Y is a propyl group which may be partially halogenated with fluorine or chlorine and Y1 is independently selected from COO, OCO, O, S, CHOH, CHF, CO, CH2; Q and Q1 are independently selected from (CH2)n wherein one or more non-adjacent methylenes may be replaced by O and N=0-20; Z and Z1 are independently selected from O, S, single covalent bond, COO, OCO; when Y and/or Y1 is CH2 then n may also be 0; Figure (2) represents any mesogenic group; and MACROCYCLE represents any macrocycle; provided that at least one of R1, R2, R3 is selected from formula (IA); k=0 or 1; g=4 or 6 or 8 or 10 or 12; l=3 or 8 provided that: if k=l, l=3 and x is selected from 6, 8, 10, 12 then g=x; if k=0, l=8 and g=4 then x=1; and further provided that G may have up to g different structures for any single compound.

    METHOD FOR MAKING CORELESS REFRACTORY FIBRES AND WHISKERS
    4.
    发明授权
    METHOD FOR MAKING CORELESS REFRACTORY FIBRES AND WHISKERS 失效
    工艺用于制备核地段耐火纤维和胡须

    公开(公告)号：EP0573424B1

    公开(公告)日：1996-02-07

    申请号：EP91913549.1

    申请日：1991-07-18

    申请人： THE SECRETARY OF STATE FOR DEFENCE IN HER BRITANNIC MAJESTY'S GOVERNMENT OF THE UNITED KINGDOM OF GREAT BRITAIN AND NORTHERN

    发明人： HOCKING, Michael, Gwyn 2 Boxgrove Road ,  SIDKY, Paulette, Shafik Glebe Lodge

    IPC分类号： H05B6/02 ,  C30B11/12 ,  C30B25/00 ,  C30B28/00

    CPC分类号： C04B35/62227 ,  C23C16/46 ,  C23C16/545 ,  C30B11/12 ,  C30B25/005

    摘要： A coreless refractory fibre is made introducing a filament (16) of a former material into a chemical vapour deposition (CVD) enclosure (10) and then heating the end (21) of the filament by means of a contactless heating source. The source comprises a conducting coil connected to an AC source in the frequency range HF to UHF and with a linear or strip conducting element (110) connected to it such that the end of the element is adjacent to the end (21) of the filament. The filament (16) is then withdrawn such that refractory material is continuously built up on its end from the chemical vapours in the enclosure to form a coreless refractory fibre. Whiskers of a coreless refractory material may be made by introducing fine particles of a catalyst material on to a platform (22) inside a CVD enclosure (25), melting the catalyst material to form droplets and then feeding CVD gases to the droplets (30) to thereby promote crystal growth by precipitation from the supersaturated liquid. The end of the precipitated material within the enclosure is heated by means of a linear conducting element vertically mounted and provided at its free end with a perpendicular conducting disc (111) adjacent and parallel to the platform (22). The platform is then moved vertically from the heat source such that the separation of the droplets (30) from the heating source (111) is maintained constant as chemical vapour is continuously deposited under the droplets (30) from the chemical vapours in the enclosure to form whiskers.

    DIGITAL PROCESSOR FOR TWO'S COMPLEMENT COMPUTATIONS
    6.
    发明授权
    DIGITAL PROCESSOR FOR TWO'S COMPLEMENT COMPUTATIONS 失效
    数字处理器的两个补充计算

    公开(公告)号：EP0471723B1

    公开(公告)日：1996-01-31

    申请号：EP90907199.5

    申请日：1990-05-02

    申请人： THE SECRETARY OF STATE FOR DEFENCE IN HER BRITANNIC MAJESTY'S GOVERNMENT OF THE UNITED KINGDOM OF GREAT BRITAIN AND NORTHERN

    发明人： McWHIRTER, John, Graham ,  WARD, Jeremy, Stuart ,  KNOWLES, Simon, Christian

    IPC分类号： G06F7/544 ,  G06F15/76

    CPC分类号： G06F15/8046 ,  G06F7/5443 ,  G06F17/16 ,  G06F2207/3892

    摘要： A digital processor (10) for two's complement computations incorporates an array (12*) of multiplier cells (12) each having the one-bit gated full adder logic function. The array (12*) has nearest-neighbour connections (16, 18, 20) containing clock-activated latches (42, 44, 50) for bit propagation. On each clock cycle, the cells (12) receive input data, carry and cumulative sum bits. Each cell (12) adds the carry and cumulative sum bits to the product of the data bit and a respective coefficient digit associated with the relevant cell (12). Data bits pass along array rows and sum bits accumulate in cascade down array columns. Carry bits are recirculated. Each coefficient digit is expressed as a sign bit and at least one magnitude bit consisting of or including a level bit. Each cell (12) includes multiplicative gating means (58, 62) responsive to the sign and level bits, and carry feedback means (60, 66) responsive to a least significant data bit flag to substitute the sign bit for a carry feedback bit. Each coefficient digit may include an additional magnitude bit expressed as a shift bit and employed to select multiplicand data bit significance, the gating means (58, 62) being responsive to flag bits to eliminate unwanted sign extension bit products. The processor (10 or 200) may include accumulating means (14 or 214) incorporating gates (90, 98 or 292, 298, 336) responsive to flag bits and arranged to eliminate unwanted result sign extension bits.

    摘要翻译： 用于二进制补码计算的数字处理器（10）包括每个具有一位门控全加器逻辑功能的乘法器单元（12）的阵列（12 *）。 阵列（12 *）具有包含用于比特传播的时钟激活锁存器（42,44,50）的最近邻居连接（16,18,20）。 在每个时钟周期中，单元（12）接收输入数据，进位和累加和位。 每个单元（12）将进位和累加和位添加到数据位和与相关单元（12）相关联的相应系数位的乘积。 数据位沿阵列行传递，总和位在级联向下阵列列中累加。 进位是循环的。 每个系数数字被表示为一个符号位和至少一个由一个电平位组成或包括一个电平位的幅度位。 每个单元（12）包括响应于符号和电平位的乘法门控装置（58,62），并且携带响应于最低有效数据位标志的反馈装置（60,66）以将符号位替换为进位反馈位。 每个系数数字可以包括表示为移位位并用于选择被乘数据位重要性的附加幅度位，门控装置（58,62）响应于标志位来消除不想要的符号扩展位产品。 处理器（10或200）可以包括累加装置（14或214），该装置响应于标志位而并入门（90,98或292,298,336）并且被安排成消除不想要的结果符号扩展位。