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    ARITHMETIC PROCESSING UNIT AND METHOD FOR CONTROLLING ARITHMETIC PROCESSING UNIT
    2.
    发明公开
    ARITHMETIC PROCESSING UNIT AND METHOD FOR CONTROLLING ARITHMETIC PROCESSING UNIT 有权
    运算处理装置及其控制方法处理单元算术

    公开(公告)号：EP2833258A1

    公开(公告)日：2015-02-04

    申请号：EP12872640.3

    申请日：2012-03-30

    申请人： FUJITSU LIMITED

    发明人： HONDO, Mikio

    IPC分类号： G06F7/556

    CPC分类号： G06F7/556 ,  G06F7/483 ,  G06F2207/483 ,  G06F2207/556

    摘要： A processor includes: an exponent generating unit (20) that generates an exponent part of a coefficient represented by a floating point number format based on a first part of received input data, the coefficient being obtained when an exponential function is decomposed into a series operation and the coefficient for the series operation; a storage unit (21) that stores a mantissa part of the coefficient; a constant generating unit (20) that reads constant data corresponding to a second part of the input data from the storage unit; and a selecting unit (23) that selects and outputs the constant data from the constant generating unit when an instruction to be executed is a coefficient calculation instruction for calculation of the coefficient of the exponential function.

    摘要翻译： 一种处理器，包括：（20）那样产生由基于接收到的输入数据的第一部分的浮点数格式表示的系数的指数部分的速率的指数生成单元，系数而获得当指数函数被分解成一系列的手术 和系数为一系列操作; 一个存储单元（21）存储做了系数的尾数部分; 常数发生部（20）做了读取恒定数据对应于从所述存储单元中的输入数据的第二部分; 和选择单元（23）做了选择并当将要执行的指令是用于指数函数的系数的计算的系数计算指令输出从常数发生部的常量数据。

    ARITHMETIC PROCESSING DEVICE AND METHOD OF CONTROLLING ARITHMETIC PROCESSING DEVICE
    3.
    发明授权
    ARITHMETIC PROCESSING DEVICE AND METHOD OF CONTROLLING ARITHMETIC PROCESSING DEVICE 有权
    算术处理设备和控制算术处理设备的方法

    公开(公告)号：EP3118737B1

    公开(公告)日：2017-12-13

    申请号：EP16179328.6

    申请日：2016-07-13

    申请人： Fujitsu Limited

    发明人： HONDO, Mikio

    IPC分类号： G06F7/556

    CPC分类号： G06F7/4833 ,  G06F7/556 ,  G06F2207/483

    摘要： An arithmetic processing device includes: a first memory configured to store values of a first coefficient of a logarithmic function, where the logarithmic function is decomposed into a series operation term and the coefficient term, depending on respective values of a first bit group included in operand data of a first instruction to calculate the value of the first coefficient; a second memory configured to store values of a second coefficient included in the series operation term depending on the respective values of the first bit group included in operand data of a second instruction to calculate the value of the second coefficient; and a selector configured to select the value of the first coefficient read from the first memory based on the execution of the first instruction and select the value of the second coefficient read from the second memory based on the execution of the second instruction.

    ARITHMETIC PROCESSING DEVICE AND METHOD OF CONTROLLING ARITHMETIC PROCESSING DEVICE
    4.
    发明公开
    ARITHMETIC PROCESSING DEVICE AND METHOD OF CONTROLLING ARITHMETIC PROCESSING DEVICE 有权
    算术处理设备及其控制方法的算术处理装置

    公开(公告)号：EP3118737A1

    公开(公告)日：2017-01-18

    申请号：EP16179328.6

    申请日：2016-07-13

    申请人： Fujitsu Limited

    发明人： HONDO, Mikio

    IPC分类号： G06F7/556

    CPC分类号： G06F7/4833 ,  G06F7/556 ,  G06F2207/483

    摘要： An arithmetic processing device includes: a first memory configured to store values of a first coefficient of a logarithmic function, where the logarithmic function is decomposed into a series operation term and the coefficient term, depending on respective values of a first bit group included in operand data of a first instruction to calculate the value of the first coefficient; a second memory configured to store values of a second coefficient included in the series operation term depending on the respective values of the first bit group included in operand data of a second instruction to calculate the value of the second coefficient; and a selector configured to select the value of the first coefficient read from the first memory based on the execution of the first instruction and select the value of the second coefficient read from the second memory based on the execution of the second instruction.

    摘要翻译： 算术处理装置，包括：被配置为存储一个对数函数，其中，所述对数函数被分解成一系列的操作项和系数项，依赖于第一位组的respectivement值的第一系数的值的第一存储器包括在操作数 第一指令以计算第一系数的值的数据; 被配置为将第二系数的存储值的第二存储器包括在一系列操作术语取决于第一比特组的值respectivement中包括的第二指令计算所述第二系数的值的操作数数据; 和选择器配置为选择从基于所述第一指令的执行的第一存储器读出的第一系数的值，并选择从基于所述第二指令的执行的第二存储器读取所述第二系数的值。

    Floating-point adder circuitry
    5.
    发明授权
    Floating-point adder circuitry 有权
    浮点加法器电路

    公开(公告)号：EP2846257B1

    公开(公告)日：2017-08-09

    申请号：EP14182740.2

    申请日：2014-08-29

    申请人： Altera Corporation

    发明人： Czajkowski, Tomasz

    IPC分类号： G06F7/485 ,  G06F7/499

    CPC分类号： G06F7/485 ,  G06F5/012 ,  G06F7/49915 ,  G06F17/10 ,  G06F2207/483

    摘要： An integrated circuit is provided that performs floating-point addition or subtraction operations involving at least three floating-point numbers. The floating-point numbers are pre-processed by dynamically extending the number of mantissa bits, determining the floating-point number with the biggest exponent, and shifting the mantissa of the other floating-point numbers to the right. Each extended mantissa has at least twice the number of bits of the mantissa entering the floating-point operation. The exact bit extension is dependent on the number of floating-point numbers to be added. The mantissas of all floating-point numbers with an exponent smaller than the biggest exponent are shifted to the right. The number of right shift bits is dependent on the difference between the biggest exponent and the respective floating-point exponent.

    摘要翻译： 提供集成电路，其执行涉及至少三个浮点数的浮点加法或减法操作。 通过动态扩展尾数位数，确定具有最大指数的浮点数，并将其他浮点数的尾数向右移位，来对浮点数进行预处理。 每个扩展后尾数至少有两次进入浮点运算的尾数位数。 确切的位扩展取决于要添加的浮点数的数量。 指数小于最大指数的所有浮点数的尾数都向右移动。 右移位的数量取决于最大指数和相应浮点指数之间的差值。

    FLOATING POINT UNIT WITH SUPPORT FOR VARIABLE LENGTH NUMBERS
    6.
    发明公开
    FLOATING POINT UNIT WITH SUPPORT FOR VARIABLE LENGTH NUMBERS 审中-公开
    GLEITKOMMAININHEIT MITUNTERSTÜTZUNGFÜRZAHLEN MIT VARIABLERLÄNGE

    公开(公告)号：EP3114558A1

    公开(公告)日：2017-01-11

    申请号：EP15711961.1

    申请日：2015-03-05

    申请人： Oracle International Corporation

    发明人： BROOKS, Jeffrey, S. ,  OLSON, Christopher, H. ,  MOGHADAM, Hesam, Fathi ,  EBERGEN, Josephus, C.

    IPC分类号： G06F7/483 ,  G06F7/491

    CPC分类号： G06F7/483 ,  G06F5/00 ,  G06F7/491 ,  G06F2207/3816 ,  G06F2207/483 ,  G06F2207/4912

    摘要： Embodiments of a processor are disclosed for performing arithmetic operations on a machine independent number format. The processor may include a floating point unit, and a number unit. The number format may include a sign/exponent block, a length block, and multiple mantissa digits. The number unit may be configured to perform an operation on two operands by converting the digit format of each mantissa digit of each operand, to perform the operation using the converted mantissa digits, and then to convert each mantissa digit of the result of the operation back into the original digit format.

    摘要翻译： 公开了一种用于对机器独立数字格式执行算术运算的处理器的实施例。 处理器可以包括浮点单元和数字单元。 数字格式可以包括符号/指数块，长度块和多个尾数位数。 数字单元可以被配置为通过转换每个操作数的每个尾数的数字格式来执行对两个操作数的操作，以使用转换的尾数来执行操作，然后将该操作结果的每个尾数转换回 转成原来的数字格式。

    HARDWARE CANCELLATION MONITOR FOR FLOATING POINT OPERATIONS
    8.
    发明公开
    HARDWARE CANCELLATION MONITOR FOR FLOATING POINT OPERATIONS 审中-公开

    公开(公告)号：EP3394719A1

    公开(公告)日：2018-10-31

    申请号：EP16879850.2

    申请日：2016-12-02

    申请人： INTEL Corporation

    发明人： ASTAFEV, Nikita ,  OULD-AHMED-VALL, Elmoustapha

    IPC分类号： G06F7/483 ,  G06F7/499 ,  G06F11/34

    CPC分类号： G06F9/3001 ,  G06F7/483 ,  G06F7/49942 ,  G06F9/30145 ,  G06F2207/483

    摘要： In an embodiment, a processor includes a plurality of cores, with at least one core including a cancellation monitor unit. The cancellation monitor unit comprises circuitry to: detect an execution of a floating point (FP) instruction in the core, wherein the execution of the FP instruction uses a set of FP inputs and generates an FP output; determine a maximum exponent value associated with the set of FP inputs to the FP instruction; subtract an exponent value of the FP output from the maximum exponent value to obtain an exponent difference; and in response to a determination that the exponent difference meets or exceeds a threshold level, increment a cancellation event count. Other embodiments are described and claimed.

    Floating-point adder circuitry
    9.
    发明公开
    Floating-point adder circuitry 有权
    Gleitkomma-Addierer-Schaltung

    公开(公告)号：EP2846257A1

    公开(公告)日：2015-03-11

    申请号：EP14182740.2

    申请日：2014-08-29

    申请人： Altera Corporation

    发明人： Czajkowski, Tomasz

    IPC分类号： G06F7/485 ,  G06F7/499

    CPC分类号： G06F7/485 ,  G06F5/012 ,  G06F7/49915 ,  G06F17/10 ,  G06F2207/483

    摘要： An integrated circuit is provided that performs floating-point addition or subtraction operations involving at least three floating-point numbers. The floating-point numbers are pre-processed by dynamically extending the number of mantissa bits, determining the floating-point number with the biggest exponent, and shifting the mantissa of the other floating-point numbers to the right. Each extended mantissa has at least twice the number of bits of the mantissa entering the floating-point operation. The exact bit extension is dependent on the number of floating-point numbers to be added. The mantissas of all floating-point numbers with an exponent smaller than the biggest exponent are shifted to the right. The number of right shift bits is dependent on the difference between the biggest exponent and the respective floating-point exponent.

    摘要翻译： 提供一种集成电路，其执行涉及至少三个浮点数的浮点加法或减法运算。 通过动态扩展尾数位数，以最大指数确定浮点数，并将其他浮点数的尾数向右移动，对浮点数进行预处理。 每个扩展尾数具有进入浮点运算的尾数的位数的至少两倍。 精确的位扩展取决于要添加的浮点数的数量。 指数小于最大指数的所有浮点数的尾数向右移动。 右移位的数量取决于最大指数和相应浮点指数之间的差异。