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    MEASURING A SECURE ENCLAVE
    2.
    发明公开
    MEASURING A SECURE ENCLAVE 有权
    MESSUNG EINER SICHEREN ENKLAVE

    公开(公告)号：EP3025266A4

    公开(公告)日：2017-03-01

    申请号：EP14829313

    申请日：2014-07-15

    申请人： INTEL CORP

    发明人： ROZAS CARLOS V ,  ANATI ITTAI ,  GERZON GIDEON ,  GUERON SHAY ,  JOHNSON SIMON P ,  MCKEEN FRANCIS X ,  SAVAGAONKAR UDAY R ,  SCARLATA VINCENT R

    IPC分类号： G06F21/00 ,  G06F9/06

    CPC分类号： H04L9/3239 ,  G06F12/1441 ,  G06F21/71 ,  G06F2221/2111

    摘要： Embodiments of an invention for measuring a secure enclave are disclosed. In one embodiment, a processor includes an instruction unit and an execution unit. The instruction unit is to receive a first, a second, and a third instruction. The execution unit is to execute the first, the second, and the third instruction. Execution of the first instruction includes initializing a measurement field in a control structure of a secure enclave with an initial value. Execution of the second instruction includes adding a region to the secure enclave. Execution of the third instruction includes measuring a subregion of the region.

    摘要翻译： 公开了用于测量安全飞地的发明的实施例。 在一个实施例中，处理器包括指令单元和执行单元。 指令单元将接收第一，第二和第三指令。 执行单元执行第一条，第二条和第三条指令。 第一指令的执行包括用初始值初始化安全区域的控制结构中的测量字段。 第二条指令的执行包括向安全飞地增加一个区域。 第三条指令的执行包括测量该地区的一个子地区。

    METHOD AND APPARATUS FOR MEMORY ENCRYPTION WITH INTEGRITY CHECK AND PROTECTION AGAINST REPLAY ATTACKS
    3.
    发明公开
    METHOD AND APPARATUS FOR MEMORY ENCRYPTION WITH INTEGRITY CHECK AND PROTECTION AGAINST REPLAY ATTACKS 有权
    方法和设备用于加密一个程序完整性测试和保护免受攻击PLAY

    公开(公告)号：EP2726991A4

    公开(公告)日：2015-04-08

    申请号：EP11868426

    申请日：2011-06-29

    申请人： INTEL CORP

    发明人： GUERON SHAY ,  SAVAGAONKAR UDAY ,  MCKEEN FRANCIS X ,  ROZAS CARLOS V ,  DURHAM DAVID M ,  DOWECK JACOB ,  MULLA OFIR ,  ANATI ITTAI ,  GREENFIELD ZVIKA ,  MAOR MOSHE

    IPC分类号： G06F12/14 ,  G06F21/00 ,  G06F21/72

    CPC分类号： G06F21/72 ,  G06F12/1408 ,  G06F21/00 ,  G06F21/64 ,  H04L9/0637 ,  H04L9/3242

    摘要： A method and apparatus to provide cryptographic integrity checks and replay protection to protect against hardware attacks on system memory is provided. A mode of operation for block ciphers enhances the standard XTS-AES mode of operation to perform memory encryption by extending a tweak to include a “time stamp” indicator. A tree-based replay protection scheme uses standard XTS-AES to encrypt contents of a cache line in the system memory. A Message-Authentication Code (MAC) for the cache line is encrypted using enhanced XTS-AES and a “time stamp” indicator associated with the cache line. The “time stamp indicator” is stored in a processor.

    摘要翻译： 一种方法和装置，以提供加密的完整性检查和重放保护，以防止硬件攻击上提供系统内存。 操作的块密码A模式增强操作的标准XTS-AES模式通过扩展一个调整为包括“时间戳”指示器来执行存储器加密。 基于树的重放保护方案采用标准的XTS-AES加密系统内存的缓存行的内容。 用于高速缓存线A的消息认证码（MAC）是使用增强XTS-AES和与高速缓存行关联的“时间戳”指示器加密。 的“时间戳指示符”被存储在处理器中。

    SM3 HASH ALGORITHM ACCELERATION PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS
    5.
    发明公开
    SM3 HASH ALGORITHM ACCELERATION PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS 审中-公开

    公开(公告)号：EP3189617A4

    公开(公告)日：2018-05-02

    申请号：EP15837850

    申请日：2015-08-14

    申请人： INTEL CORP

    发明人： GUERON SHAY ,  KRASNOV VLAD

    IPC分类号： H04L9/06 ,  G06F9/30

    CPC分类号： H04L9/0643 ,  G06F9/30007 ,  G06F9/30036 ,  G06F9/3895 ,  G09C1/00 ,  H04L2209/125

    摘要： A processor includes a decode unit to decode an SM3 two round state word update instruction. The instruction is to indicate one or more source packed data operands. The source packed data operand(s) are to have eight 32-bit state words Aj, Bj, Cj, Dj, Ej, Fj, Gj, and Hj that are to correspond to a round (j) of an SM3 hash algorithm. The source packed data operand(s) are also to have a set of messages sufficient to evaluate two rounds of the SM3 hash algorithm. An execution unit coupled with the decode unit is operable, in response to the instruction, to store one or more result packed data operands, in one or more destination storage locations. The result packed data operand(s) are to have at least four two-round updated 32-bit state words Aj+2, Bj+2, Ej+2, and Fj+2, which are to correspond to a round (j+2) of the SM3 hash algorithm.