公开(公告)号：EP4425340A2

公开(公告)日：2024-09-04

申请号：EP24189785.9

申请日：2019-04-23

申请人： Micron Technology, Inc.

发明人： HASBUN, Robert, Nasry ,  GANS, Dean, D. ,  DARUWALLA, Sharookh

IPC分类号： G06F12/02

CPC分类号： G06F13/1689 ,  G06F13/36 ,  G11C7/1045 ,  G11C2207/227220130101 ,  G11C7/1063 ,  G11C11/2293 ,  G06F12/0859 ,  G06F12/0868 ,  G06F12/0893 ,  G06F12/0246

摘要： Systems and method for a latency indication in a memory system or sub-system are described. A controller of a memory system may transmit a signal pulse to a host over a first duration in response to receiving a first command from the host indicating to wait for a second duration. The interface controller may transmit such an indication when a latency associated with performing the first command is likely to be greater than a latency anticipated by the host. The interface controller may determine a second duration based on a status of buffer or a status of memory device, or both. The interface controller may use a pin designated and configured to transmit a command or control information to the host when transmitting a signal including an indication of a time delay. The interface controller may use a quantity, duration, or pattern of pulses to indicate a duration of a time delay.

公开(公告)号：EP4195207B1

公开(公告)日：2024-08-28

申请号：EP22211794.7

申请日：2022-12-06

IPC分类号： G11C11/22 ,  G11C13/00 ,  H10N70/20

CPC分类号： G11C11/221 ,  G11C13/0007 ,  G11C11/2275 ,  G11C11/2273 ,  G11C2013/004520130101 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/7920130101 ,  G11C2213/8220130101 ,  G11C2013/005420130101 ,  G11C13/0061 ,  G11C11/2293 ,  G11C13/0026 ,  G11C11/005 ,  H10N70/24 ,  H10N70/8833 ,  H10N70/826

公开(公告)号：EP4396817A1

公开(公告)日：2024-07-10

申请号：EP22865676.5

申请日：2022-08-11

申请人： MICRON TECHNOLOGY, INC.

发明人： VIMERCATI, Daniele

IPC分类号： G11C11/4074 ,  G11C11/4096 ,  G11C11/22

CPC分类号： G11C11/2273 ,  G11C11/2255 ,  G11C11/221 ,  G11C11/2253 ,  G11C11/2293

公开(公告)号：EP4287030A3

公开(公告)日：2024-05-15

申请号：EP23203962.8

申请日：2019-04-23

申请人： Micron Technology, Inc.

发明人： HASBUN, Robert, Nasry ,  GANS, Dean, D. ,  DARUWALLA, Sharookh

IPC分类号： G06F3/06 ,  G06F13/16 ,  G11C7/22 ,  G06F12/0855 ,  G06F12/0868 ,  G06F12/0893 ,  G06F12/02

CPC分类号： G06F13/1689 ,  G06F13/36 ,  G11C7/1045 ,  G11C2207/227220130101 ,  G11C7/1063 ,  G11C11/2293 ,  G06F12/0859 ,  G06F12/0868 ,  G06F12/0893 ,  G06F12/0246

摘要： Methods, systems, and devices for a latency indication in a memory system or subsystem are described. An interface controller of a memory system may transmit an indication of a time delay (e.g., a wait signal) to a host in response to receiving an access command from the host. The interface controller may transmit such an indication when a latency associated with performing the access command is likely to be greater than a latency anticipated by the host. The interface controller may determine a time delay based on a status of buffer or a status of memory device, or both. The interface controller may use a pin designated and configured to transmit a command or control information to the host when transmitting a signal including an indication of a time delay. The interface controller may use a quantity, duration, or pattern of pulses to indicate a duration of a time delay.

公开(公告)号：EP4374373A1

公开(公告)日：2024-05-29

申请号：EP22846744.5

申请日：2022-07-07

申请人： MICRON TECHNOLOGY, INC.

发明人： KITAGAWA, Makoto

IPC分类号： G11C11/22

CPC分类号： G11C11/2273 ,  G11C11/2293 ,  G11C11/4091 ,  G11C11/4076 ,  G11C11/4094 ,  G11C11/2255 ,  G11C11/2257 ,  G11C11/4085 ,  G11C11/4097

公开(公告)号：EP2744108A3

公开(公告)日：2015-06-10

申请号：EP13197354.7

申请日：2013-12-16

申请人： Palo Alto Research Center Incorporated

发明人： Schwartz, David Eric

IPC分类号： H03K3/355 ,  G11C11/22 ,  H03K19/017

CPC分类号： G11C11/221 ,  G11C11/22 ,  G11C11/2293 ,  H03K3/355 ,  H03K19/01714

摘要： A pulse generator circuit with ferroelectric memory element is disclosed that is optimized for printed, solution-processed thin film transistor processing. In certain embodiments, the circuit comprises dual thin film transistors (14, 16) that operate as a diode and resistor, respectively. Optionally, a third thin film transistor may be provided to operate as a pass transistor in response to an enable signal. The elements of the circuit are configured such that a rising pulse on an input node (IN) triggers an output pulse on an output node (OUT) in the manner of a monostable multivibrator. The ferroelectric memory element is coupled to the output node such that a pulse on the output node may change a state of the ferroelectric memory element

公开(公告)号：EP2744108A2

公开(公告)日：2014-06-18

申请号：EP13197354.7

申请日：2013-12-16

申请人： Palo Alto Research Center Incorporated

发明人： Schwartz, David Eric

IPC分类号： H03K3/355 ,  G11C11/22

CPC分类号： G11C11/221 ,  G11C11/22 ,  G11C11/2293 ,  H03K3/355 ,  H03K19/01714

摘要： A pulse generator circuit with ferroelectric memory element is disclosed that is optimized for printed, solution-processed thin film transistor processing. In certain embodiments, the circuit comprises dual thin film transistors (14, 16) that operate as a diode and resistor, respectively. Optionally, a third thin film transistor may be provided to operate as a pass transistor in response to an enable signal. The elements of the circuit are configured such that a rising pulse on an input node (IN) triggers an output pulse on an output node (OUT) in the manner of a monostable multivibrator. The ferroelectric memory element is coupled to the output node such that a pulse on the output node may change a state of the ferroelectric memory element

摘要翻译： 公开了一种具有铁电存储元件的脉冲发生器电路，其被优化用于印刷，溶液处理的薄膜晶体管处理。 在某些实施例中，电路包括分别作为二极管和电阻器工作的双薄膜晶体管（14,16）。 可选地，可以提供第三薄膜晶体管以响应于使能信号而作为传输晶体管操作。 电路的元件被配置为使得输入节点（IN）上的上升脉冲以单稳态多谐振荡器的方式触发输出节点（OUT）上的输出脉冲。 铁电存储元件耦合到输出节点，使得输出节点上的脉冲可以改变铁电存储元件的状态

公开(公告)号：EP3427265B1

公开(公告)日：2024-05-01

申请号：EP17763926.7

申请日：2017-03-07

IPC分类号： G11C11/22 ,  G11C7/10 ,  G11C8/18

CPC分类号： G11C11/2257 ,  G11C11/2273 ,  G11C11/221 ,  G11C11/2293 ,  G11C7/1042 ,  G11C8/18

公开(公告)号：EP2744108B1

公开(公告)日：2016-05-25

申请号：EP13197354.7

申请日：2013-12-16

申请人： Palo Alto Research Center Incorporated

发明人： Schwartz, David Eric

IPC分类号： H03K3/355 ,  G11C11/22 ,  H03K19/017

CPC分类号： G11C11/221 ,  G11C11/22 ,  G11C11/2293 ,  H03K3/355 ,  H03K19/01714

公开(公告)号：EP2647009A4

公开(公告)日：2016-05-11

申请号：EP11844741

申请日：2011-11-17

申请人： RADIANT TECHNOLOGIES INC

发明人： EVANS JOSEPH T ,  WARD CALVIN B

IPC分类号： G11C11/22 ,  G11C11/56 ,  G11C27/00

CPC分类号： G11C11/221 ,  G11C11/2259 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/2293 ,  G11C11/5657 ,  G11C27/005

摘要： A ferroelectric memory having a plurality of ferroelectric memory cells, each ferroelectric memory cell including a ferroelectric capacitor is disclosed. The ferroelectric memory includes read and write lines and a plurality of ferroelectric memory cell select buses, one select bus corresponding to each of the ferroelectric memory cells. Each of the ferroelectric memory cells includes first and second gates for connecting the ferroelectric memory cell to the read line and the write line, respectively, in response to signals on the ferroelectric memory cell select bus corresponding to that ferroelectric memory cell. A write circuit causes a charge to be stored in the ferroelectric capacitor of the ferroelectric memory cell currently connected to the write line, the charge having a value determined by a data value having at least three states. A read circuit measures the charge stored in the ferroelectric capacitor of the ferroelectric memory cell currently connected to the read line to generate an output value, the output value corresponding to one of the states.

摘要翻译： 公开了具有多个强电介质存储单元的铁电存储器，每个强电介质存储单元包括铁电电容器。 铁电存储器包括读取和写入线和多个铁电存储器单元选择总线，每个铁电存储单元相应的一个选择总线。 每个铁电存储单元包括用于分别响应于与该铁电存储单元相对应的铁电存储单元选择总线上的信号而将铁电存储单元连接到读取线和写入线的第一和第二栅极。 写入电路使得电荷存储在当前连接到写入线的强电介质存储单元的铁电电容器中，电荷具有由具有至少三个状态的数据值确定的值。 读取电路测量存储在当前连接到读取线的铁电存储器单元的铁电电容器中的电荷，以产生与其中一个状态对应的输出值。