公开(公告)号：EP3076422B1

公开(公告)日：2018-10-31

申请号：EP15815488.0

申请日：2015-05-25

申请人： Fuji Electric Co., Ltd.

发明人： FUJII, Takeshi ,  SATO, Mariko ,  INAMOTO, Takuro

IPC分类号： H01L21/28 ,  H01L29/45 ,  H01L29/16

CPC分类号： H01L21/0485 ,  H01L29/1606 ,  H01L29/1608 ,  H01L29/45

摘要： After a graphene layer (11) is formed on a surface of a p-type silicon carbide semiconductor region (1), a metal electrode (2) is formed on a surface of the graphene layer (11) to form a dipole at a junction interface of the p-type silicon carbide semiconductor region (1) and the metal electrode (2). As a result, a potential difference generated at the junction interface of the p-type silicon carbide semiconductor region (1) and the metal electrode (2) is reduced and a contact between the p-type silicon carbide semiconductor region (1) and the metal electrode (2) is achieved as a low-resistance ohmic contact. The p-type silicon carbide semiconductor region (1) has a carrier concentration of at least 1×10 16 /cm 3 . The graphene layer (11) has a single-layer structure or a stacked structure of three or less layers. Coverage of the graphene layer (11) on the p-type silicon carbide semiconductor region (1) is at least 30% of a surface area of the p-type silicon carbide semiconductor region (1). As a result, the low-resistance ohmic contact can be formed with high reproducibility.

公开(公告)号：EP2284867B1

公开(公告)日：2018-05-09

申请号：EP10014514.3

申请日：2008-03-14

申请人： Nissan Motor Co., Ltd.

发明人： Tanimoto, Satoshi

IPC分类号： H01L21/04 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L29/45 ,  H01L29/94 ,  H01L29/739

CPC分类号： H01L29/7802 ,  H01L21/0485 ,  H01L21/049 ,  H01L29/41766 ,  H01L29/45 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/7395 ,  H01L29/94

摘要： A MOS type SiC semiconductor device having high reliability and a longer lifespan against TDDB of a gate oxide film is disclosed. The semiconductor device includes a MOS (metal-oxide-semiconductor) structure having a silicon carbide (SiC) substrate, a polycrystalline Si gate electrode, a gate oxide film interposed between the SiC substrate and the polycrystalline Si gate electrode and formed by thermally oxidizing a surface of the SiC substrate, and an ohmic contact electrically contacted with the SiC substrate. The semiconductor device further includes a polycrystalline Si thermally-oxidized film formed by oxidizing a surface of the polycrystalline Si gate electrode. The gate oxide film has a thickness of 20 nm or less, advantageously 15 nm or less.

公开(公告)号：EP2149154B1

公开(公告)日：2018-04-25

申请号：EP08825948.6

申请日：2008-03-31

申请人： Cree, Inc.

发明人： DAS, Mrinal Kanti ,  ZHANG, Qingchun ,  CLAYTON, John, M., Jr. ,  DONOFRIO, Matthew

IPC分类号： H01L29/739 ,  H01L21/04 ,  H01L21/268 ,  H01L23/482 ,  H01L29/10 ,  H01L29/66

CPC分类号： H01L29/66068 ,  H01L21/0475 ,  H01L21/0485 ,  H01L21/268 ,  H01L23/4827 ,  H01L29/1095 ,  H01L29/7395 ,  H01L2224/04026 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/00

摘要： A silicon carbide power device is fabricated by forming a p-type silicon carbide epitaxial layer on an n-type silicon carbide substrate, and forming a silicon carbide power device structure on the p-type silicon carbide epitaxial layer. The n-type silicon carbide substrate is at least partially removed, so as to expose the p-type silicon carbide epitaxial layer. An ohmic contact is formed on at least some of the p-type silicon carbide epitaxial layer that is exposed. By at least partially removing the n-type silicon carbide substrate and forming an ohmic contact on the p-type silicon carbide epitaxial layer, the disadvantages of using a p-type substrate may be reduced or eliminated. Related structures are also described.

公开(公告)号：EP2883239B8

公开(公告)日：2018-02-14

申请号：EP13802420.3

申请日：2013-09-24

申请人： TOYOTA JIDOSHA KABUSHIKI KAISHA

发明人： FUJIWARA, Hirokazu ,  SOEJIMA, Narumasa

IPC分类号： H01L21/04

CPC分类号： H01L21/0485 ,  H01L21/30604 ,  H01L21/32133

摘要： A manufacturing method of a semiconductor device includes: forming an electric metal layer by depositing metal as art electrode material on an inside of an opening of an insulating layer on a surface of an SiC semiconductor substrate; widening a gap between an inner wall surface in an opening formed in the insulating layer and the electrode metal layer by etching the insulating layer after the electrode metal layer is formed; and forming an ohmic contact between the electrode metal layer and the SiC semiconductor substrate by heating the SiC semiconductor substrate and the metal electrode layer after the insulating layer is etched.

公开(公告)号：EP3134914A1

公开(公告)日：2017-03-01

申请号：EP14889954.5

申请日：2014-04-23

申请人： United Silicon Carbide Inc.

发明人： HOSTETLER, John L.

IPC分类号： H01L21/268

CPC分类号： H01L21/268 ,  H01L21/046 ,  H01L21/0485

摘要： Systems and methods for semiconductor wafer processing include irradiating a surface of a semiconductor wafer with a laser beam of sufficient energy to alter a band gap of semiconductor material thereby melting a portion of the wafer to generate a graphitic layer area. A metal layer is then depositing on the surface to create ohmic contacts at the area that where melted by the laser.

摘要翻译： 用于半导体晶片处理的系统和方法包括用足够能量的激光束照射半导体晶片的表面以改变半导体材料的带隙，从而熔化晶片的一部分以产生石墨层面积。 然后将金属层沉积在表面上以在由激光熔化的区域处形成欧姆接触。

公开(公告)号：EP2320466B1

公开(公告)日：2016-11-23

申请号：EP09808072.4

申请日：2009-08-20

申请人： Showa Denko K.K.

发明人： MATSUSE, Akihiro ,  YANO, Kotaro

IPC分类号： H01L29/47 ,  H01L29/861 ,  H01L29/872

CPC分类号： H01L21/0485 ,  H01L21/0495 ,  H01L29/0619 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/47 ,  H01L29/6606 ,  H01L29/872

公开(公告)号：EP3076422A1

公开(公告)日：2016-10-05

申请号：EP15815488.0

申请日：2015-05-25

申请人： Fuji Electric Co., Ltd.

发明人： FUJII, Takeshi ,  SATO, Mariko ,  INAMOTO, Takuro

IPC分类号： H01L21/28

CPC分类号： H01L21/0485 ,  H01L29/1606 ,  H01L29/1608 ,  H01L29/45

摘要： After a graphene layer (11) is formed on a surface of a p-type silicon carbide semiconductor region (1), a metal electrode (2) is formed on a surface of the graphene layer (11) to form a dipole at a junction interface of the p-type silicon carbide semiconductor region (1) and the metal electrode (2). As a result, a potential difference generated at the junction interface of the p-type silicon carbide semiconductor region (1) and the metal electrode (2) is reduced and a contact between the p-type silicon carbide semiconductor region (1) and the metal electrode (2) is achieved as a low-resistance ohmic contact. The p-type silicon carbide semiconductor region (1) has a carrier concentration of at least 1×10 16 /cm 3 . The graphene layer (11) has a single-layer structure or a stacked structure of three or less layers. Coverage of the graphene layer (11) on the p-type silicon carbide semiconductor region (1) is at least 30% of a surface area of the p-type silicon carbide semiconductor region (1). As a result, the low-resistance ohmic contact can be formed with high reproducibility.

摘要翻译： 在p型碳化硅半导体区域（1）的表面上形成石墨烯层（11）之后，在石墨烯层（11）的表面上形成金属电极（2），以在连接处形成偶极子 p型碳化硅半导体区域（1）和金属电极（2）的界面。 结果，在p型碳化硅半导体区域（1）和金属电极（2）的接合界面处产生的电位差减小，并且p型碳化硅半导体区域（1）和 金属电极（2）被实现为低电阻欧姆接触。 p型碳化硅半导体区域（1）的载流子浓度为1×10 16 / cm 3以上。 石墨烯层（11）具有三层或更少层的单层结构或堆叠结构。 p型碳化硅半导体区域（1）上的石墨烯层（11）的覆盖率为p型碳化硅半导体区域（1）的表面积的至少30％。 结果，可以以高再现性形成低电阻欧姆接触。

公开(公告)号：EP3043376A1

公开(公告)日：2016-07-13

申请号：EP14842165.4

申请日：2014-08-08

申请人： Fuji Electric Co., Ltd. ,  National Institute of Advanced Industrial Science and Technology

发明人： UTSUMI, Makoto ,  SAKAI, Yoshiyuki ,  FUKUDA, Kenji ,  HARADA, Shinsuke ,  OKAMOTO, Mitsuo

IPC分类号： H01L21/28 ,  H01L21/26 ,  H01L21/336 ,  H01L29/06 ,  H01L29/12 ,  H01L29/78

CPC分类号： H01L29/1608 ,  H01L21/0485 ,  H01L21/283 ,  H01L21/324 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/66477 ,  H01L29/7802

摘要： An infrared ray absorbing film (8) is selectively formed on a surface of an n - -type silicon carbide substrate (1). A p-type contact pattern (9) including aluminum and a Ni pattern (10) including nickel are selectively formed in this order on the n - -type silicon carbide substrate (1), in an area excluding an area in which the infrared ray absorbing film (8) is formed. The n - -type silicon carbide substrate (1) is thereafter heated using a rapid annealing process to form an ohmic electrode that includes the p-type contact pattern (9) and the Ni pattern (10) converted into silicide.

摘要翻译： 一个红外线吸收的电影（8）选择性地形成的n的表面上 - 型碳化硅衬底（1）。 型碳化硅衬底，其中所述红外线的（1），在一个区域不包括区域 - 一个p-型接触图案（9）包括铝和镍图案（10）包括镍在第n按此顺序有选择地形成 吸收膜（8）形成。 n - 型碳化硅衬底（1）使用快速退火处理，以形成在欧姆电极做之后加热包括在p型接触图案（9）与Ni图案（10）转化为硅化物。

公开(公告)号：EP2830085A4

公开(公告)日：2015-11-25

申请号：EP13765262

申请日：2013-03-15

申请人： AISIN SEIKI

发明人： TANIGAWA TATSUYA ,  OTA MICHIHARU

IPC分类号： H01L21/28 ,  B23K26/062 ,  B23K26/36 ,  H01L29/417

CPC分类号： H01L21/268 ,  B23K26/0006 ,  B23K26/0078 ,  B23K26/0084 ,  B23K26/0624 ,  B23K26/0648 ,  B23K26/0853 ,  B23K2201/40 ,  B23K2203/56 ,  B82Y10/00 ,  H01L21/0485 ,  H01L21/28537 ,  H01L29/0619 ,  H01L29/0665 ,  H01L29/1608 ,  H01L29/34 ,  H01L29/417 ,  H01L29/812 ,  H01L29/872

公开(公告)号：EP2927962A1

公开(公告)日：2015-10-07

申请号：EP13859209.2

申请日：2013-10-21

申请人： Sumitomo Electric Industries, Ltd.

发明人： HIYOSHI, Toru ,  WADA, Keiji

IPC分类号： H01L29/47 ,  H01L29/06 ,  H01L29/872

CPC分类号： H01L29/872 ,  H01L21/0485 ,  H01L21/0495 ,  H01L29/045 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0661 ,  H01L29/1608 ,  H01L29/47 ,  H01L29/6606 ,  H01L29/66143

摘要： A first main surface (P1) of a silicon carbide substrate (10) has a flat surface (FT) located in an element portion (CL) and a side wall surface (ST) located in a termination portion (TM). The silicon carbide substrate (10) has an impurity layer (11) having a portion located at each of the flat surface (FT) of the first main surface (P1) and a second main surface (P2). On the flat surface (FT), a Schottky electrode (31) is in contact with the impurity layer (11). On the second main surface (P2), a counter electrode (42) is in contact with the impurity layer (11). An insulating film (21) covers the side wall surface (ST). The side wall surface (ST) is inclined by not less than 50° and not more than 80° relative to a {000-1} plane. This suppresses the leakage current of a silicon carbide semiconductor device (101).

摘要翻译： 碳化硅衬底（10）的第一主表面（P1）具有位于元件部分（CL）中的平坦表面（FT）和位于终端部分（TM）中的侧壁表面（ST）。 碳化硅衬底（10）具有杂质层（11），该杂质层具有位于第一主表面（P1）和第二主表面（P2）的每个平坦表面（FT）处的部分。 在平坦表面（FT）上，肖特基电极（31）与杂质层（11）接触。 在第二主表面（P2）上，对电极（42）与杂质层（11）接触。 绝缘膜（21）覆盖侧壁面（ST）。 侧壁表面（ST）相对于{000-1}平面倾斜不小于50°且不大于80°。 这抑制了碳化硅半导体器件（101）的漏电流。