公开(公告)号：EP2564415B1

公开(公告)日：2018-12-26

申请号：EP11724287.5

申请日：2011-04-26

申请人： Pilegrowth Tech S.r.l.

发明人： VAN KANEL, Hans ,  MIGLIO, Leonida

IPC分类号： H01L21/02

CPC分类号： H01L21/02639 ,  H01L21/0237 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02521 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/0265

摘要： Structures and methods for producing active layer stacks of lattice matched, lattice mismatched and thermally mismatched semiconductor materials, with low threading dislocation densities, no layer cracking and minimized wafer bowing, by using epitaxial growth onto elevated substrate regions in a mask-less process.

公开(公告)号：EP3327094A1

公开(公告)日：2018-05-30

申请号：EP17202400.2

申请日：2017-11-17

申请人： United Technologies Corporation

发明人： SCHMIDT, Wayde R ,  SHEEDY, Paul

IPC分类号： C09D11/03 ,  C04B35/571 ,  C09D11/101 ,  C09D11/102 ,  C09D183/16 ,  C08L83/16

CPC分类号： C09D11/102 ,  B41J2/01 ,  C04B35/5603 ,  C04B35/571 ,  C04B35/58 ,  C04B35/584 ,  C04B2235/36 ,  C04B2235/3817 ,  C04B2235/3852 ,  C04B2235/402 ,  C04B2235/404 ,  C04B2235/421 ,  C04B2235/422 ,  C04B2235/425 ,  C04B2235/428 ,  C04B2235/447 ,  C04B2235/483 ,  C04B2235/5288 ,  C08L83/16 ,  C09D11/03 ,  C09D11/101 ,  C09D183/16 ,  C23C4/131 ,  C23C4/134 ,  H01L21/02112 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02216 ,  H01L21/02222 ,  H01L21/02521 ,  H01L21/02529 ,  H01L21/0254 ,  H01L21/02546 ,  H01L21/02628 ,  H01L21/02667

摘要： A printable material in ink form for forming electronic and structural components capable of high temperature performance includes a polymeric or oligomeric ceramic precursor, a filler material and an optional liquid carrier. The ceramic precursor materials may be silicon carbide, silicon oxycarbide, silicon nitride, silicon carbonitride, silicon oxycarbonitride, gallium containing group 13 oligomeric compounds and mixtures thereof. The ceramic precursor may be deposited by a direct ink writing (DIW) process.

公开(公告)号：EP3320565A1

公开(公告)日：2018-05-16

申请号：EP16736196.3

申请日：2016-07-08

申请人： COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES

发明人： DUPRE, Cécilia ,  BOGUMILOWICZ, Yann

IPC分类号： H01L31/0687 ,  H01L31/0352 ,  H01L31/054 ,  H01L21/02

CPC分类号： H01L31/0687 ,  H01L21/02381 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/0262 ,  H01L21/02639 ,  H01L31/0352 ,  H01L31/0543 ,  Y02E10/52 ,  Y02E10/544 ,  Y02P70/521

摘要： The invention relates to a photovoltaic cell and to a method for manufacturing a photovoltaic cell, comprising: a silicon substrate (1) forming a p-n junction; a so-called "barrier" layer (4) made of transparent dielectric material, the barrier layer (4) being deposited on the substrate (1), the barrier layer (4) having a plurality of recesses (5) passing through same; a layer of III-V material (20, 20a, 20b) forming a p-n junction being deposited in each recess (5); a so-called "intermediate" layer (9) made of transparent dielectric material, the intermediate layer (9) being deposited on the barrier layer (4); a layer of microlenses (10) deposited on the intermediate layer (9), the layer of microlenses (10) comprising a plurality of microlenses (11), each microlens (11) having a focal point located in each recess (5).

公开(公告)号：EP3118950A4

公开(公告)日：2018-02-14

申请号：EP15761533

申请日：2015-03-11

申请人： FURUKAWA ELECTRIC CO LTD

发明人： IWAMI MASAYUKI ,  ISHII HIROTATSU ,  IWAI NORIHIRO ,  MATSUDA TAKEYOSHI ,  KASUKAWA AKIHIKO ,  ISHIKAWA TAKUYA ,  KAWAKITA YASUMASA ,  KAJI EISAKU

IPC分类号： H01S5/343 ,  H01L21/02 ,  H01L29/201 ,  H01L29/36 ,  H01L29/778 ,  H01L29/868 ,  H01L31/0304 ,  H01L31/036 ,  H01L31/105 ,  H01S5/22 ,  H01S5/227 ,  H01S5/30 ,  H01S5/32 ,  H01S5/323

CPC分类号： H01S5/34313 ,  H01L21/02546 ,  H01L21/02576 ,  H01L21/02609 ,  H01L29/045 ,  H01L29/201 ,  H01L29/205 ,  H01L29/36 ,  H01L29/7784 ,  H01L29/7787 ,  H01L29/868 ,  H01L31/03046 ,  H01L31/036 ,  H01L31/105 ,  H01S5/2224 ,  H01S5/227 ,  H01S5/3086 ,  H01S5/309 ,  H01S5/32 ,  H01S5/32358 ,  H01S5/32366 ,  H01S5/3434 ,  H01S5/34373

摘要： A semiconductor laser device includes a well layer and a barrier layer formed of a III-V group semiconductor crystal containing As as a primary component. A V group element other than As has been introduced at a concentration of 0.02 to 5% into a V group site of the III-V group semiconductor crystal in at least one of the well layer and the barrier layer. A III group site of the III-V group semiconductor crystal in at least one of the well layer and the barrier layer contains Al. A semiconductor laser device suppressing generation of defects in a bulk of a semiconductor crystal and having less variation of characteristics is thereby provided.

公开(公告)号：EP3238265A1

公开(公告)日：2017-11-01

申请号：EP14909228.0

申请日：2014-12-23

申请人： Intel Corporation

发明人： GARDNER, Sanaz K. ,  RACHMADY, Willy ,  METZ, Matthew V. ,  DEWEY, Gilbert ,  KAVALIEROS, Jack T. ,  MOHAPATRA, Chandra S. ,  MURTHY, Anand S. ,  RAHHAL-ORABI, Nadia ,  ZELICK, Nancy M. ,  FRENCH, Marc C. ,  GHANI, Tahir

IPC分类号： H01L29/78 ,  H01L21/20

CPC分类号： H01L29/66742 ,  B82Y10/00 ,  H01L21/02392 ,  H01L21/02546 ,  H01L21/02603 ,  H01L21/823412 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/20 ,  H01L29/42392 ,  H01L29/66469 ,  H01L29/66522 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78681 ,  H01L29/78696

摘要： An embodiment includes a device comprising: first and second fins adjacent one another and each including channel and subfin layers, the channel layers having bottom surfaces directly contacting upper surfaces of the subfin layers; wherein (a) the bottom surfaces are generally coplanar with one another and are generally flat; (b) the upper surfaces are generally coplanar with one another and are generally flat; and (c) the channel layers include an upper material and the subfin layers include a lower III-V material different from the upper III-V material. Other embodiments are described herein.

摘要翻译： 一个实施例包括一种装置，包括：彼此相邻并且各自包括沟道层和亚鳍层的第一和第二鳍片，沟道层具有与亚鳍层的上表面直接接触的底表面; 其中（a）底面大体上彼此共面且大致平坦; （b）上表面通常彼此共面并且大致平坦; 和（c）沟道层包括上部III-V族材料，亚层包括不同于上部III-V族材料的下部III-V族材料。 这里描述了其他实施例。

公开(公告)号：EP3238229A1

公开(公告)日：2017-11-01

申请号：EP15834680.9

申请日：2015-12-23

申请人： Integrated Solar

发明人： BUGGE, Renato ,  MYRVÅGNES, Geir

IPC分类号： H01L21/02 ,  H01L31/0304 ,  H01L31/18

CPC分类号： H01L21/02381 ,  H01L21/02433 ,  H01L21/02463 ,  H01L21/02466 ,  H01L21/02516 ,  H01L21/02521 ,  H01L21/02546 ,  H01L21/02609 ,  H01L31/0735 ,  H01L31/1844 ,  H01L31/1852 ,  Y02E10/544

摘要： The present invention relates to a method of manufacturing semiconductor materials comprising interface layers of group III-V materials in combination with Si substrates. Especially the present invention is related to a method of manufacturing semiconductor materials comprising GaAs in combination with Si(111) substrates, wherein residual strain due to different thermal expansion coefficient of respective materials is counteracted by introducing added layer(s) compensating the residual strain.

摘要翻译： 本发明涉及一种制造半导体材料的方法，所述半导体材料包括与Si衬底组合的III-V族材料的界面层。 特别地，本发明涉及一种制造包含与Si（111）衬底结合的GaAs的半导体材料的方法，其中通过引入补偿残余应变的附加层来抵消由于相应材料的不同热膨胀系数引起的残余应变。

公开(公告)号：EP3123497A4

公开(公告)日：2017-11-01

申请号：EP14886790

申请日：2014-03-28

申请人： INTEL CORP

发明人： METZ MATTHEW V ,  KAVALIEROS JACK T ,  DEWEY GILBERT ,  RACHMADY WILLY ,  CHU-KUNG BENJAMIN ,  RADOSAVLJEVIC MARKO ,  THEN HAN WUI ,  PILLARISETTY RAVI ,  CHAU ROBERT S

IPC分类号： H01L21/20 ,  H01L21/18

CPC分类号： H01L29/205 ,  H01L21/02381 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02466 ,  H01L21/02502 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02639 ,  H01L21/76224 ,  H01L21/823431 ,  H01L29/1054 ,  H01L29/66522 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7851

摘要： An embodiment includes a III-V material based device, comprising: a first III-V material based buffer layer on a silicon substrate; a second III-V material based buffer layer on the first III-V material based buffer layer, the second III-V material including aluminum; and a III-V material based device channel layer on the second III-V material based buffer layer. Another embodiment includes the above subject matter and the first and second III-V material based buffer layers each have a lattice parameter equal to the III-V material based device channel layer. Other embodiments are included herein.

公开(公告)号：EP3198053A1

公开(公告)日：2017-08-02

申请号：EP15781035.9

申请日：2015-09-25

申请人： Philipps Universität Marburg

发明人： VON HAENISCH, Carsten ,  VOLZ, Kerstin ,  STOLZ, Wolfgang ,  STERZER, Eduard ,  BEYER, Andreas ,  KEIPER, Dominik ,  RINGLER, Benjamin

IPC分类号： C23C16/30 ,  C07F9/46 ,  C07F9/50 ,  C07F9/72 ,  C07F9/90

CPC分类号： H01L21/02538 ,  C07F9/46 ,  C07F9/504 ,  C07F9/72 ,  C07F9/904 ,  C23C16/22 ,  C23C16/301 ,  H01L21/0254 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/0262

摘要： The invention provides the use of at least one binary group 15 element compound of the general formula R1R2E-E′R3R4 (I) or R5E(E′R6R7)2 (II) as the educt in a vapor deposition process. In this case, R1, R2, R3 and R4 are independently selected from the group consisting of H, an alkyl radical (C1-C10) and an aryl group, and E and E′ are independently selected from the group consisting of N, P, As, Sb and Bi. This use excludes hydrazine and its derivatives. The binary group 15 element compounds according to the invention allow the realization of a reproducible production and/or deposition of multinary, homogeneous and ultrapure 13/15 semiconductors of a defined combination at relatively low process temperatures. This makes it possible to completely waive the use of an organically substituted nitrogen compound such as 1.1 dimethyl hydrazine as the nitrogen source, which drastically reduces nitrogen contaminations—compared to the 13/15 semiconductors and/or 13/15 semiconductor layers produced with the known production methods.

摘要翻译： 本发明提供了至少一种通式R 1 R 2 E-E'R 3 R 4（I）或R 5 E（E'R 6 R 7）2（II）的二元15族元素化合物作为气相沉积工艺中的离析物的用途。 在这种情况下，R1，R2，R3和R4独立地选自由H，烷基（C1-C10）和芳基组成的组，并且E和E'独立地选自N，P ，As，Sb和Bi。 该用途不包括肼及其衍生物。 根据本发明的二元族15元素化合物允许在相对较低的处理温度下实现限定组合的多元，均质和超纯13/15半导体的可再现生产和/或沉积。 这使得可以完全放弃使用有机取代的氮化合物如1,1-二甲基肼作为氮源，与用已知的方法生产的13/15半导体和/或13/15半导体层相比，其显着降低氮污染 生产方法。

公开(公告)号：EP3031084A4

公开(公告)日：2017-02-22

申请号：EP14833768

申请日：2014-08-06

申请人： FIRST SOLAR INC

发明人： GARABEDIAN RAFFI ,  MALIK ROGER ,  THEIL JEREMY ,  TRIVEDI JIGISH ,  YU MING

IPC分类号： H01L31/0304 ,  C23C16/455 ,  C23C16/54

CPC分类号： H01L31/0304 ,  C23C14/243 ,  C23C14/568 ,  C23C16/22 ,  H01L21/02546 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/64 ,  H01L21/67173 ,  H01L21/6776 ,  H01L31/03046 ,  H01L31/0693 ,  H01L31/18 ,  H01L31/184 ,  H01L2221/67 ,  Y02E10/544 ,  Y02P70/521

公开(公告)号：EP3123497A1

公开(公告)日：2017-02-01

申请号：EP14886790.6

申请日：2014-03-28

申请人： Intel Corporation

发明人： METZ, Matthew, V. ,  KAVALIEROS, Jack, T. ,  DEWEY, Gilbert ,  RACHMADY, Willy ,  CHU-KUNG, Benjamin ,  RADOSAVLJEVIC, Marko ,  THEN, Han Wui ,  PILLARISETTY, Ravi ,  CHAU, Robert, S.

IPC分类号： H01L21/20 ,  H01L21/18

CPC分类号： H01L29/205 ,  H01L21/02381 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02466 ,  H01L21/02502 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02639 ,  H01L21/76224 ,  H01L21/823431 ,  H01L29/1054 ,  H01L29/66522 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7851

摘要： An embodiment includes a III-V material based device, comprising: a first III-V material based buffer layer on a silicon substrate; a second III-V material based buffer layer on the first III-V material based buffer layer, the second III-V material including aluminum; and a III-V material based device channel layer on the second III-V material based buffer layer. Another embodiment includes the above subject matter and the first and second III-V material based buffer layers each have a lattice parameter equal to the III-V material based device channel layer. Other embodiments are included herein.

摘要翻译： 实施例包括基于III-V材料的器件，包括：在硅衬底上的基于第一III-V材料的缓冲层; 在第一III-V材料基缓冲层上的第二III-V材料基缓冲层，第二III-V材料包括铝; 以及在第二III-V材料基缓冲层上的基于III-V材料的器件沟道层。 另一个实施例包括上述主题，第一和第二III-V材料基缓冲层各自具有等于基于III-V材料的器件沟道层的晶格参数。 其他实施例包括在本文中。