公开(公告)号：EP2286450B1

公开(公告)日：2011-10-19

申请号：EP09757723.3

申请日：2009-05-12

申请人： ST Microelectronics (Rousset) SAS

发明人： FORNARA, Pascal

IPC分类号： H01L21/8246 ,  H01L27/02 ,  H01L27/112 ,  H01L27/115 ,  G11C16/00 ,  G11C17/00

CPC分类号： H01L27/1052 ,  H01L27/112 ,  H01L27/11213 ,  H01L27/11519 ,  H01L27/11521

摘要： A non-volatile memory including at least first and second memory cells each including a storage MOS transistor with dual gates and an insulation layer provided between the two gates. The insulation layer of the storage transistor of the second memory cell includes at least one portion that is less insulating than the insulation layer of the storage transistor of the first memory cell.

公开(公告)号：EP3121818A1

公开(公告)日：2017-01-25

申请号：EP15178040.0

申请日：2015-07-23

申请人： Synopsys, Inc.

发明人： Rawat, Anil Singh ,  Singh, Pritender

IPC分类号： G11C17/10 ,  G11C17/12 ,  G11C17/18

CPC分类号： G11C17/12 ,  G06F17/5045 ,  G11C17/10 ,  G11C17/123 ,  G11C17/126 ,  G11C17/18 ,  H01L27/11213

摘要： A method to program bitcells (11, ..., mn) of a ROM array (10) uses different programming cells (0a, ..., 0h, 1a, ..., 1d) for programming the bitcells (11, ..., mn) with a first or second data item. A first bitcell (11) is programmed by means of a selected programming cell, wherein the programming cell is selected in dependence on operating the memory array (10) as a flipped or a non-flipped memory in multi-bank instance. All other bitcells (12, 13) located in the same column (C1) as the first bitcell (11) and subsequent rows (R2, R3) are programmed by selected programming cells, wherein the selection of the programming cells is dependent on operating the memory array (10) as a flipped or a non-flipped memory in multi-bank instance and the programming state of the programming cells used for the previously programmed bitcells in the same column (C1).

摘要翻译： 用于对ROM阵列（10）的位单元（11，...，mn）进行编程的方法使用不同的编程单元（0a，...，0h，1a，...，1d）来编程位单元（11，...， ..，mn）与第一或第二数据项。 第一位单元（11）通过所选择的编程单元进行编程，其中根据多存储器实例中的翻转存储器或非翻转存储器操作存储器阵列（10）来选择编程单元。 位于与第一位单元（11）和后续行（R2，R3）相同的列（C1）中的所有其它位单元（12,13）由选定的编程单元编程，其中编程单元的选择取决于操作 存储器阵列（10）作为多组实例中的翻转存储器或非翻转存储器，以及用于同一列（C1）中的先前编程的位单元的编程单元的编程状态。

公开(公告)号：EP1455394B1

公开(公告)日：2018-04-11

申请号：EP02749361.8

申请日：2002-07-24

申请人： Samsung Electronics Co., Ltd.

发明人： SHIMODA, Tatsuya ,  UTSUNOMIYA, Sumio

IPC分类号： H01L27/12 ,  H01L27/00 ,  H01L21/52 ,  G02F1/133 ,  G09F9/00 ,  H01L27/118 ,  H01L27/13 ,  B82Y10/00 ,  H01L21/683 ,  B82Y30/00 ,  H01L29/66 ,  H01L27/108 ,  H01L27/11 ,  H01L27/112 ,  H01L27/115 ,  H01L27/11502 ,  H01L27/11517 ,  H01L27/11585 ,  H01L27/1159 ,  H05K3/04 ,  H01L51/56 ,  G02F1/13 ,  H01L27/32

CPC分类号： H01L27/1266 ,  B82Y10/00 ,  B82Y30/00 ,  G02F2001/13613 ,  H01L21/6835 ,  H01L21/6836 ,  H01L27/10844 ,  H01L27/11 ,  H01L27/11213 ,  H01L27/11502 ,  H01L27/11517 ,  H01L27/11585 ,  H01L27/1159 ,  H01L27/118 ,  H01L27/1214 ,  H01L27/13 ,  H01L27/3244 ,  H01L29/66757 ,  H01L29/66772 ,  H01L51/56 ,  H01L2221/68318 ,  H01L2221/68322 ,  H01L2221/6835 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2221/68368 ,  H01L2221/68381 ,  H01L2224/95 ,  H01L2225/06562 ,  H05K3/046

摘要： A transfer method comprising a step of forming a plurality of transferred bodies on a transfer origin substrate, and a step of applying energy to partial regions corresponding to the transferred bodies to be transferred, and transferring these transferred bodies corresponding to the partial regions onto a transfer destination substrate. A plurality of transferred bodies such as devices or circuits that are to be disposed on a transfer destination substrate with spaces therebetween can be manufactured integrated together on a transfer origin substrate, and hence compared with the case that the transferred bodies are formed on the transfer destination substrate directly, the amount of materials used in the manufacture of the transferred bodies can be reduced, the area efficiency can be greatly improved, and a transfer destination substrate on which a large number of devices or circuits are disposed in scattered locations can be manufactured efficiently and cheaply.

公开(公告)号：EP2286450A1

公开(公告)日：2011-02-23

申请号：EP09757723.3

申请日：2009-05-12

申请人： ST Microelectronics (Rousset) SAS

发明人： FORNARA, Pascal

IPC分类号： H01L21/8246 ,  H01L27/02 ,  H01L27/112 ,  H01L27/115 ,  G11C16/00 ,  G11C17/00

CPC分类号： H01L27/1052 ,  H01L27/112 ,  H01L27/11213 ,  H01L27/11519 ,  H01L27/11521

摘要： A non-volatile memory including at least first and second memory cells each including a storage MOS transistor with dual gates and an insulation layer provided between the two gates. The insulation layer of the storage transistor of the second memory cell includes at least one portion that is less insulating than the insulation layer of the storage transistor of the first memory cell.

摘要翻译： 一种非易失性存储器，至少包括第一和第二存储单元，每个存储单元包括具有双栅极的存储MOS晶体管和设置在两个栅极之间的绝缘层。 第二存储器单元的存储晶体管的绝缘层包括绝缘层比第一存储器单元的存储晶体管的绝缘层更少的至少一个部分。

公开(公告)号：EP3121818B1

公开(公告)日：2018-08-22

申请号：EP15178040.0

申请日：2015-07-23

申请人： Synopsys, Inc.

发明人： Rawat, Anil Singh ,  Singh, Pritender

IPC分类号： G11C17/10 ,  G11C17/12 ,  G11C17/18 ,  G06F17/50 ,  H01L27/112

CPC分类号： G11C17/12 ,  G06F17/5045 ,  G11C17/10 ,  G11C17/123 ,  G11C17/126 ,  G11C17/18 ,  H01L27/11213

摘要： A method to program bitcells (11, ..., mn) of a ROM array (10) uses different programming cells (0a, ..., 0h, 1a, ..., 1d) for programming the bitcells (11, ..., mn) with a first or second data item. A first bitcell (11) is programmed by means of a selected programming cell, wherein the programming cell is selected in dependence on operating the memory array (10) as a flipped or a non-flipped memory in multi-bank instance. All other bitcells (12, 13) located in the same column (C1) as the first bitcell (11) and subsequent rows (R2, R3) are programmed by selected programming cells, wherein the selection of the programming cells is dependent on operating the memory array (10) as a flipped or a non-flipped memory in multi-bank instance and the programming state of the programming cells used for the previously programmed bitcells in the same column (C1).

公开(公告)号：EP2565924B1

公开(公告)日：2018-01-10

申请号：EP12190201.9

申请日：2002-07-24

申请人： Samsung Electronics Co., Ltd.

发明人： Shimoda, Tatsuya ,  Utsunomiya, Sumio

IPC分类号： H01L27/11502 ,  H01L27/11517 ,  H01L27/11585 ,  H01L27/1159 ,  H01L21/683 ,  H01L27/12 ,  H01L27/00 ,  H01L21/52 ,  G02F1/133 ,  G09F9/00 ,  H01L27/118 ,  H01L27/13 ,  H05K3/04 ,  H01L27/11 ,  B82Y30/00 ,  B82Y10/00 ,  H01L27/108 ,  H01L21/336 ,  H01L27/112 ,  G02F1/136 ,  H01L51/56 ,  H01L27/32

CPC分类号： H01L27/1266 ,  B82Y10/00 ,  B82Y30/00 ,  G02F2001/13613 ,  H01L21/6835 ,  H01L21/6836 ,  H01L27/10844 ,  H01L27/11 ,  H01L27/11213 ,  H01L27/11502 ,  H01L27/11517 ,  H01L27/11585 ,  H01L27/1159 ,  H01L27/118 ,  H01L27/1214 ,  H01L27/13 ,  H01L27/3244 ,  H01L29/66757 ,  H01L29/66772 ,  H01L51/56 ,  H01L2221/68318 ,  H01L2221/68322 ,  H01L2221/6835 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2221/68368 ,  H01L2221/68381 ,  H01L2224/95 ,  H01L2225/06562 ,  H05K3/046

摘要： A transfer method comprising a step of forming a plurality of transferred bodies on a transfer origin substrate, and a step of applying energy to partial regions corresponding to the transferred bodies to be transferred, and transferring these transferred bodies corresponding to the partial regions onto a transfer destination substrate. A plurality of transferred bodies such as devices or circuits that are to be disposed on a transfer destination substrate with spaces therebetween can be manufactured integrated together on a transfer origin substrate, and hence compared with the case that the transferred bodies are formed on the transfer destination substrate directly, the amount of materials used in the manufacture of the transferred bodies can be reduced, the area efficiency can be greatly improved, and a transfer destination substrate on which a large number of devices or circuits are disposed in scattered locations can be manufactured efficiently and cheaply.

公开(公告)号：EP1455394A1

公开(公告)日：2004-09-08

申请号：EP02749361.8

申请日：2002-07-24

申请人： SEIKO EPSON CORPORATION

发明人： SHIMODA, Tatsuya, c/o SEIKO EPSON CORPORATION ,  UTSUNOMIYA, Sumio, c/o SEIKO EPSON CORPORATION

IPC分类号： H01L27/12 ,  H01L27/00 ,  H01L21/52 ,  G02F1/133 ,  G09F9/00

CPC分类号： H01L27/1266 ,  B82Y10/00 ,  B82Y30/00 ,  G02F2001/13613 ,  H01L21/6835 ,  H01L21/6836 ,  H01L27/10844 ,  H01L27/11 ,  H01L27/11213 ,  H01L27/11502 ,  H01L27/11517 ,  H01L27/11585 ,  H01L27/1159 ,  H01L27/118 ,  H01L27/1214 ,  H01L27/13 ,  H01L27/3244 ,  H01L29/66757 ,  H01L29/66772 ,  H01L51/56 ,  H01L2221/68318 ,  H01L2221/68322 ,  H01L2221/6835 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2221/68368 ,  H01L2221/68381 ,  H01L2224/95 ,  H01L2225/06562 ,  H05K3/046

摘要： A transfer method comprising a step of forming a plurality of transferred bodies on a transfer origin substrate, and a step of applying energy to partial regions corresponding to the transferred bodies to be transferred, and transferring these transferred bodies corresponding to the partial regions onto a transfer destination substrate. A plurality of transferred bodies such as devices or circuits that are to be disposed on a transfer destination substrate with spaces therebetween can be manufactured integrated together on a transfer origin substrate, and hence compared with the case that the transferred bodies are formed on the transfer destination substrate directly, the amount of materials used in the manufacture of the transferred bodies can be reduced, the area efficiency can be greatly improved, and a transfer destination substrate on which a large number of devices or circuits are disposed in scattered locations can be manufactured efficiently and cheaply.

公开(公告)号：EP0712136A2

公开(公告)日：1996-05-15

申请号：EP95117328.5

申请日：1995-11-03

申请人： TOYOTA JIDOSHA KABUSHIKI KAISHA

发明人： Ishida, Shoji ,  Nakano, Kenji ,  Kashiwaya, Motofumi ,  Inoue, Masataka

IPC分类号： G11C17/14 ,  H01L21/8246

CPC分类号： B82Y10/00 ,  B82Y40/00 ,  G11C17/12 ,  G11C17/14 ,  H01J37/3174 ,  H01J2237/31761 ,  H01L27/11213

摘要： A nonvolatile memory producing apparatus has a data computing section 31, an electron patterning section 33 for patterning a wafer 3 by using an electron beam, a control section 32 for controlling +the electron patterning section 33 on the basis of the result from the data computing section 31. The data computing section 31 prepares binary codes for individual IC chips formed on the wafer 3, and generates coordinate regarding the wafer 3 and the IC chips. The data computing section 31 computes direct draw data for each IC chip based on the binary codes, and generates direct pattern data based on the binary codes and the direct draw data. The control section 32 and the electron-beam patterning section 33 cooperate to perform direct electron-beam patterning on the IC chips in accordance with the pattern data.

公开(公告)号：EP2565924A3

公开(公告)日：2014-02-26

申请号：EP12190201.9

申请日：2002-07-24

申请人： Samsung Electronics Co., Ltd.

发明人： Shimoda, Tatsuya ,  Utsunomiya, Sumio

IPC分类号： H01L27/12 ,  H01L27/00 ,  H01L21/52 ,  G02F1/133 ,  G09F9/00 ,  H01L21/683 ,  H01L27/115 ,  H01L27/118 ,  H01L27/13 ,  H05K3/04 ,  H01L27/11 ,  B82Y30/00 ,  B82Y10/00 ,  H01L27/108 ,  H01L29/66 ,  H01L27/112 ,  H01L51/56 ,  H01L27/32 ,  G02F1/136

CPC分类号： H01L27/1266 ,  B82Y10/00 ,  B82Y30/00 ,  G02F2001/13613 ,  H01L21/6835 ,  H01L21/6836 ,  H01L27/10844 ,  H01L27/11 ,  H01L27/11213 ,  H01L27/11502 ,  H01L27/11517 ,  H01L27/11585 ,  H01L27/1159 ,  H01L27/118 ,  H01L27/1214 ,  H01L27/13 ,  H01L27/3244 ,  H01L29/66757 ,  H01L29/66772 ,  H01L51/56 ,  H01L2221/68318 ,  H01L2221/68322 ,  H01L2221/6835 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2221/68368 ,  H01L2221/68381 ,  H01L2224/95 ,  H01L2225/06562 ,  H05K3/046

摘要： A transfer method comprising a step of forming a plurality of transferred bodies 2a on a transfer origin substrate 1, and a step of applying energy to partial regions corresponding to the transferred bodies to be transferred, and transferring these transferred bodies corresponding to the partial regions onto a transfer destination substrate 3. A plurality of transferred bodies such as devices or circuits that are to be disposed on a transfer destination substrate with spaces therebetween can be manufactured integrated together on a transfer origin substrate, and hence compared with the case that the transferred bodies are formed on the transfer destination substrate directly, the amount of materials used in the manufacture of the transferred bodies can be reduced, the area efficiency can be greatly improved, and a transfer destination substrate on which a large number of devices or circuits are disposed in scattered locations can be manufactured efficiently and cheaply.

公开(公告)号：EP2565924A2

公开(公告)日：2013-03-06

申请号：EP12190201.9

申请日：2002-07-24

申请人： Samsung Electronics Co., Ltd.

发明人： Shimoda, Tatsuya ,  Utsunomiya, Sumio

IPC分类号： H01L27/12 ,  H01L27/00 ,  H01L21/52 ,  G02F1/133 ,  G09F9/00 ,  H01L21/683 ,  H01L27/115 ,  H01L27/118 ,  H01L27/13 ,  H05K3/04 ,  H01L27/11 ,  B82Y30/00 ,  B82Y10/00 ,  H01L27/108 ,  H01L29/66 ,  H01L27/112

CPC分类号： H01L27/1266 ,  B82Y10/00 ,  B82Y30/00 ,  G02F2001/13613 ,  H01L21/6835 ,  H01L21/6836 ,  H01L27/10844 ,  H01L27/11 ,  H01L27/11213 ,  H01L27/11502 ,  H01L27/11517 ,  H01L27/11585 ,  H01L27/1159 ,  H01L27/118 ,  H01L27/1214 ,  H01L27/13 ,  H01L27/3244 ,  H01L29/66757 ,  H01L29/66772 ,  H01L51/56 ,  H01L2221/68318 ,  H01L2221/68322 ,  H01L2221/6835 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2221/68368 ,  H01L2221/68381 ,  H01L2224/95 ,  H01L2225/06562 ,  H05K3/046

摘要： A transfer method comprising a step of forming a plurality of transferred bodies 2a on a transfer origin substrate 1, and a step of applying energy to partial regions corresponding to the transferred bodies to be transferred, and transferring these transferred bodies corresponding to the partial regions onto a transfer destination substrate 3. A plurality of transferred bodies such as devices or circuits that are to be disposed on a transfer destination substrate with spaces therebetween can be manufactured integrated together on a transfer origin substrate, and hence compared with the case that the transferred bodies are formed on the transfer destination substrate directly, the amount of materials used in the manufacture of the transferred bodies can be reduced, the area efficiency can be greatly improved, and a transfer destination substrate on which a large number of devices or circuits are disposed in scattered locations can be manufactured efficiently and cheaply.

摘要翻译： 包括在传送源衬底1上形成转移体2a中的多个步骤，并且将能量施加到对应于所述转移体部分区域的步骤的传输方法被传送，并且传递环论文转移机构对应于该部分区域走上 传送目的地衬底转移机构3的多个：如装置或电路也将被在一个转移目的地的基板与空间有设置在可以在传输源的衬底来制造集成在一起，并且因此，使用情况相比做了转移体 形成在直接传输目的地的基板，能够减少在转移体的制造中使用的材料的量，面积效率可以大大提高，并在其上设置大量的器件或电路的传送目的地的基板 位置分散能够便宜且高效地进行制造。