公开(公告)号：EP2779232A3

公开(公告)日：2014-12-03

申请号：EP14160005.6

申请日：2014-03-14

申请人： Renesas Electronics Corporation

发明人： Kajiwara, Ryoichi ,  Nakajo, Takuya ,  Arai, Katsuo ,  Yato, Yuichi ,  Oka, Hiroi ,  Hozoji, Hiroshi

IPC分类号： H01L23/488 ,  H01L23/49 ,  H01L21/60 ,  H01L23/31 ,  H01L23/495

CPC分类号： H01L23/49 ,  H01L21/50 ,  H01L23/293 ,  H01L23/295 ,  H01L23/3107 ,  H01L23/3192 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49562 ,  H01L23/49582 ,  H01L23/562 ,  H01L23/564 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L29/1608 ,  H01L29/2003 ,  H01L2224/0381 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/0603 ,  H01L2224/291 ,  H01L2224/29111 ,  H01L2224/29118 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29294 ,  H01L2224/29439 ,  H01L2224/2949 ,  H01L2224/3011 ,  H01L2224/3201 ,  H01L2224/32013 ,  H01L2224/32058 ,  H01L2224/32059 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45565 ,  H01L2224/45616 ,  H01L2224/45639 ,  H01L2224/45644 ,  H01L2224/45664 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/48724 ,  H01L2224/48739 ,  H01L2224/48744 ,  H01L2224/48755 ,  H01L2224/48824 ,  H01L2224/48839 ,  H01L2224/48844 ,  H01L2224/48855 ,  H01L2224/48997 ,  H01L2224/4903 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2224/83055 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/83439 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/8392 ,  H01L2224/83951 ,  H01L2224/85205 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/8592 ,  H01L2224/85951 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2924/00011 ,  H01L2924/10272 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/06 ,  H01L2924/00012 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/01013 ,  H01L2924/01051 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/83205

摘要： A semiconductor device (20, 24, 29, 32, 35, 38) includes a die pad (6), a wide gap semiconductor chip (SiC or GaN) (1) mounted on the die pad (6), a porous first sintered Ag layer (16) bonding the die pad (6) and the chip (1), and a reinforcing resin portion (17) covering a surface of the first sintered Ag layer (16) and a part of a side surface of the chip (1) and formed in a fillet shape. The semiconductor device (20, 24, 29, 32, 35, 38) further includes electrodes (1g, 1h, 2, 3, 4) on its main (1a) and back (1b) surfaces, the electrodes (1g, 1h, 2, 3, 4) being electrically connected to leads (7, 9, 11, 39), wherein the electrical connection at the front side is a wire (18, 19, 25, 26) connection and the electrical connection at the back side is the first sintered Ag layer (16). A porous second sintered Ag layer (36) or a second resin portion (30) reinforces the wire bonding portion on the electrode (1g, 2, 3). The semiconductor device (20, 24, 29, 32, 35, 38) further includes a sealing body (third resin) (14) which covers the chip (1), the first sintered Ag layer (16), and a part of the die pad (6).

摘要翻译： 一种半导体器件（20,24,29,32,35,38）包括管芯焊盘（6），安装在管芯焊盘（6）上的宽带隙半导体芯片（SiC或GaN）（1），多孔第一烧结体 （6）和芯片（1）接合的Ag层（16）;以及覆盖第一烧结Ag层（16）的表面和芯片侧面的一部分的加强树脂部分（17） 1）并形成圆角形状。 半导体器件（20,24,29,32,35,38）还包括在其主（1a）和背（1b）表面上的电极（1g，1h，2,3,4），电极（1g，1h， （2,3,4）电连接到引线（7,9,11,39），其中在正面的电连接是导线（18,19,25,26）连接并且背面的电连接 是第一个烧结Ag层（16）。 多孔的第二烧结Ag层（36）或第二树脂部分（30）加强电极（1g，2,3）上的引线键合部分。 半导体器件（20,24,29,32,35,38）还包括覆盖芯片（1），第一烧结Ag层（16）和第一烧结Ag层（16）的一部分的密封体（第三树脂） 芯片焊盘（6）。

公开(公告)号：EP3231266A1

公开(公告)日：2017-10-18

申请号：EP14907696.0

申请日：2014-12-09

申请人： Intel Corporation

发明人： MAY, Robert ,A. ,  BOYAPATI, Sri Ranga Sai ,  ALUR, Amruthavalli, P. ,  SOBIESKI, Daniel, N.

IPC分类号： H05K3/46 ,  H01L23/12

CPC分类号： C22C9/00 ,  C22C27/04 ,  H01L23/12 ,  H01L23/49 ,  H01L23/49866 ,  H01L2224/0401 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81203 ,  H01L2224/81205 ,  H01L2224/81815 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/00014

摘要： Microelectronic substrates having copper alloy conductive routes to reduce warpage due to differing coefficient of thermal expansion of the components used to form the microelectronic substrates. In one embodiment, the conductive routes of the microelectronic substrate may comprise an alloy of copper and an alloying metal of tungsten, molybdenum, or a combination thereof. In another embodiment, the conductive routes of the microelectronic substrate may comprise an alloy of copper, an alloying metal of tungsten, molybdenum, or a combination thereof, and a co-deposition metal of nickel, cobalt, iron, or a combination thereof. In still another embodiment, the copper alloy conductive routes may have copper concentrations which are graded therethrough, which may enable better pattern formation during a subtractive etching process used to form the copper alloy conductive routes.

摘要翻译： 具有铜合金导电路径的微电子衬底，以减少由于用于形成微电子衬底的组件的不同热膨胀系数而导致的翘曲。 在一个实施例中，微电子衬底的导电路线可以包括铜和钨，钼或其组合的合金化金属的合金。 在另一个实施例中，微电子衬底的导电路径可以包括铜，钨，钼或其组合的合金化金属以及镍，钴，铁或其组合的共沉积金属的合金。 在又一个实施例中，铜合金导电线路可以具有通过其中渐变的铜浓度，这可以在用于形成铜合金导电路线的减去蚀刻工艺期间实现更好的图案形成。

公开(公告)号：EP2648212A1

公开(公告)日：2013-10-09

申请号：EP10860383.8

申请日：2010-11-29

申请人： TOYOTA JIDOSHA KABUSHIKI KAISHA

发明人： TANAKA Hiroaki

IPC分类号： H01L21/60 ,  H01L21/3205 ,  H01L23/52 ,  H01L29/739 ,  H01L29/78

CPC分类号： H01L23/498 ,  H01L23/49 ,  H01L24/05 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L29/417 ,  H01L29/41741 ,  H01L29/7397 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05557 ,  H01L2224/05624 ,  H01L2224/45014 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48132 ,  H01L2224/4847 ,  H01L2224/48491 ,  H01L2224/49175 ,  H01L2224/85205 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/3511 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/206

摘要： A semiconductor device disclosed in this description has a semiconductor substrate including an element region in which a semiconductor element is formed, and an upper surface electrode formed on an upper surface of the element region of the semiconductor substrate. The upper surface electrode has a first thickness region and a second thickness region which is thicker than the first thickness region, and a bonding wire is bonded on the second thickness region.

摘要翻译： 本说明书中公开的半导体器件具有包括形成有半导体元件的元件区域和形成在半导体衬底的元件区域的上表面上的上表面电极的半导体衬底。 上表面电极具有第一厚度区域和比第一厚度区域厚的第二厚度区域，并且接合线接合在第二厚度区域上。

公开(公告)号：EP0349095B1

公开(公告)日：1999-05-19

申请号：EP89202084.3

申请日：1983-02-23

申请人： HITACHI, LTD.

发明人： Onuki, Jin ,  Suwa, Masateru ,  Koizumi, Masahiro ,  Iizuka, Tomio ,  Tamamura, Takeo

IPC分类号： H01L21/607 ,  H01L23/49 ,  B23K20/00

CPC分类号： H01L24/85 ,  B23K20/007 ,  B23K2201/42 ,  H01L23/3107 ,  H01L23/3135 ,  H01L23/48 ,  H01L23/49 ,  H01L23/4952 ,  H01L23/49582 ,  H01L24/43 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/78 ,  H01L2224/05624 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/43 ,  H01L2224/43848 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45164 ,  H01L2224/45166 ,  H01L2224/45169 ,  H01L2224/4517 ,  H01L2224/4518 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4845 ,  H01L2224/48465 ,  H01L2224/48472 ,  H01L2224/4851 ,  H01L2224/48624 ,  H01L2224/48639 ,  H01L2224/48655 ,  H01L2224/48724 ,  H01L2224/48739 ,  H01L2224/48755 ,  H01L2224/48799 ,  H01L2224/48839 ,  H01L2224/48855 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/85043 ,  H01L2224/85045 ,  H01L2224/85075 ,  H01L2224/85181 ,  H01L2224/85201 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85424 ,  H01L2224/85439 ,  H01L2224/85455 ,  H01L2224/85948 ,  H01L2224/92247 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01061 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  Y10T428/12431 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/48824 ,  H01L2924/00015 ,  H01L2924/20105 ,  H01L2924/20106 ,  H01L2924/20107 ,  H01L2924/20108 ,  H01L2924/20109 ,  H01L2924/2011 ,  H01L2924/20111 ,  H01L2924/2075 ,  H01L2924/01049 ,  H01L2924/01006

公开(公告)号：EP0088557A2

公开(公告)日：1983-09-14

申请号：EP83300956.6

申请日：1983-02-23

申请人： Hitachi, Ltd.

发明人： Onuki, Jin ,  Suwa, Masateru ,  Koizumi, Masahiro ,  Iizuka, Tomio ,  Tamamura, Takeo

IPC分类号： H01L23/29

CPC分类号： H01L24/85 ,  B23K20/007 ,  B23K2201/42 ,  H01L23/3107 ,  H01L23/3135 ,  H01L23/48 ,  H01L23/49 ,  H01L23/4952 ,  H01L23/49582 ,  H01L24/43 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/78 ,  H01L2224/05624 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/43 ,  H01L2224/43848 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45164 ,  H01L2224/45166 ,  H01L2224/45169 ,  H01L2224/4517 ,  H01L2224/4518 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4845 ,  H01L2224/48465 ,  H01L2224/48472 ,  H01L2224/4851 ,  H01L2224/48624 ,  H01L2224/48639 ,  H01L2224/48655 ,  H01L2224/48724 ,  H01L2224/48739 ,  H01L2224/48755 ,  H01L2224/48799 ,  H01L2224/48839 ,  H01L2224/48855 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/85043 ,  H01L2224/85045 ,  H01L2224/85075 ,  H01L2224/85181 ,  H01L2224/85201 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85424 ,  H01L2224/85439 ,  H01L2224/85455 ,  H01L2224/85948 ,  H01L2224/92247 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01061 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  Y10T428/12431 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/48824 ,  H01L2924/00015 ,  H01L2924/20105 ,  H01L2924/20106 ,  H01L2924/20107 ,  H01L2924/20108 ,  H01L2924/20109 ,  H01L2924/2011 ,  H01L2924/20111 ,  H01L2924/2075 ,  H01L2924/01049 ,  H01L2924/01006

摘要： A resin encapsulated semiconductor device comprises a semiconductor element (3), a conductive terminal (4) and a wire (1) connecting the element (3) and the terminal (4). A thermosetting resin (12) encapsulates the component hermetically to protect the device from a mechanical stress and ambient atmosphere. In order to achieve good bonding of the wire (1) at its ends, the wire (1) is made of a metal (e.g. Al) having in the annealed state a maximum elongation at room temperature of not more than 60%, the wire having been annealed before the bonding.

摘要翻译： 树脂封装的半导体器件包括半导体元件（3），导电端子（4）和连接元件（3）和端子（4）的导线（1）。 热固性树脂（12）密封该部件，以保护装置免受机械应力和环境气氛的影响。 为了在其端部实现线（1）的良好的接合，线（1）由处于退火状态的金属（例如Al）制成，室温下的最大伸长率不超过60％，线 在接合之前已经退火。

公开(公告)号：EP4404254A3

公开(公告)日：2024-09-04

申请号：EP24172898.9

申请日：2019-04-10

申请人： Semtech Corporation

发明人： AINSWORTH, Christopher David

IPC分类号： H01L25/16 ,  H01L23/522 ,  H01L23/045 ,  H01L23/49

CPC分类号： H01L23/5223 ,  H01L25/167 ,  H01L23/045 ,  H01L23/49 ,  H01L2224/4825720130101 ,  H01L2224/0555420130101 ,  H01L28/87 ,  H01L28/88 ,  H01L2224/7326520130101

摘要： A semiconductor device comprises a semiconductor die and an integrated capacitor formed over the semiconductor die. The integrated capacitor is configured to receive a high voltage signal. A transimpedance amplifier is formed in the semiconductor die. An avalanche photodiode is disposed over or adjacent to the semiconductor die. The integrated capacitor is coupled between the avalanche photodiode and a ground node. A resistor is coupled between a high voltage input and the avalanche photodiode. The resistor is an integrated passive device (IPD) formed over the semiconductor die. A first terminal of the integrated capacitor is coupled to a ground voltage node. A second terminal of the integrated capacitor is coupled to a voltage greater than 20 volts. The integrated capacitor comprises a plurality of interdigitated fingers in one embodiment. In another embodiment, the integrated capacitor comprises a plurality of vertically aligned plates.

公开(公告)号：EP4372807A1

公开(公告)日：2024-05-22

申请号：EP22207915.4

申请日：2022-11-16

申请人： Infineon Technologies AG

发明人： BAYER, Christoph ,  FUEGL, Michael ,  SINGER, Frank ,  MEYER, Thorsten ,  CRAES, Fabian ,  GRASSMANN, Andreas ,  OTTO, Frederik

IPC分类号： H01L23/48 ,  H01L25/07 ,  H01L21/48 ,  H01L23/31 ,  H01L23/49 ,  H01L23/373

CPC分类号： H01L25/072 ,  H01L23/3735 ,  H01L23/49 ,  H01L2224/3222520130101 ,  H01L2224/3223820130101 ,  H01L24/29 ,  H01L24/32 ,  H01L2224/8319220130101 ,  H01L2224/8319320130101 ,  H01L2224/7326520130101 ,  H01L2224/2900520130101 ,  H01L2224/2915720130101 ,  H01L2224/2914720130101 ,  H01L2224/2912420130101 ,  H01L2224/3201320130101 ,  H01L2224/4822720130101 ,  H01L24/83 ,  H01L21/4814 ,  H01L23/3121 ,  H01L2224/274520130101 ,  H01L2224/8320320130101 ,  H01L2224/2916320130101 ,  H01L23/49811 ,  H01L23/373 ,  H01L23/3736 ,  H01L23/24 ,  H01L23/053

摘要： A substrate arrangement comprises a first metallization layer (111), a plurality of nanowires (612) arranged on a surface of the first metallization layer (111), and at least one component (20, 4) arranged on the first metallization layer (111) such that a first subset of the plurality of nanowires (612) is arranged between the first metallization layer (111) and the at least one component (20, 4), wherein the plurality of nanowires (612) is evenly distributed over a section of the surface area or over the entire surface area of the first metallization layer (111), each of the plurality of nanowires (612) comprises a first end and a second end, wherein the first end of each of the plurality nanowires (612) is inseparably connected to the surface of the first metallization layer (111), the second end of each nanowire of the first subset is inseparably connected to a surface of one of the at least one component (20, 4) such that the first subset of nanowires (612) forms a permanent connection between the first metallization layer (111) and the at least one component (20, 4), the at least one component (20, 4) comprises at least one semiconductor body (20), and the number of nanowires (612) comprised in the first subset of nanowires (612) is less than the number of nanowires (612) comprised in the plurality of nanowires.

公开(公告)号：EP3401957A1

公开(公告)日：2018-11-14

申请号：EP17170743.3

申请日：2017-05-12

申请人： Infineon Technologies AG

发明人： Kuehle, Elmar ,  Nomann, Marianna

IPC分类号： H01L23/498

CPC分类号： H01L21/4875 ,  H01L21/481 ,  H01L23/142 ,  H01L23/15 ,  H01L23/49 ,  H01L23/49811 ,  H01L23/49833 ,  H01L24/48 ,  H01L2224/48175

摘要： A power semiconductor module arrangement comprising a base plate to be arranged in a housing, a contact element configured to, when the base plate is arranged within the housing, provide an electrical connection between the inside and the outside of the housing, and a connecting element configured to connect the contact element to the base plate. The connecting element comprises a first electrically insulating layer, a second electrically insulating layer configured to attach the contact element to the first electrically insulating layer, and a third electrically insulating layer configured to attach the first electrically insulating layer to the base plate.

公开(公告)号：EP3281218A1

公开(公告)日：2018-02-14

申请号：EP16726297.1

申请日：2016-05-23

申请人： Siemens Aktiengesellschaft

发明人： STEGMEIER, Stefan ,  BAUEREGGER, Hubert ,  SOMMER, Volkmar

IPC分类号： H01L21/60 ,  H01L23/492 ,  H01L23/495 ,  H01L23/367

CPC分类号： H01L23/49 ,  C25D3/38 ,  C25D5/18 ,  C25D21/14 ,  H01L23/3733 ,  H01L23/3735 ,  H01L23/4922 ,  H01L23/49513 ,  H01L23/49537 ,  H01L23/49562 ,  H01L23/49568 ,  H01L23/49811 ,  H01L23/50 ,  H01L24/05 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/75 ,  H01L24/77 ,  H01L24/82 ,  H01L24/83 ,  H01L24/84 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/04026 ,  H01L2224/04034 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/24105 ,  H01L2224/24227 ,  H01L2224/24245 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/3207 ,  H01L2224/32227 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/37005 ,  H01L2224/37111 ,  H01L2224/37124 ,  H01L2224/37139 ,  H01L2224/37144 ,  H01L2224/37147 ,  H01L2224/37155 ,  H01L2224/37166 ,  H01L2224/3719 ,  H01L2224/37211 ,  H01L2224/37224 ,  H01L2224/37239 ,  H01L2224/37244 ,  H01L2224/37247 ,  H01L2224/37255 ,  H01L2224/37266 ,  H01L2224/3729 ,  H01L2224/373 ,  H01L2224/37395 ,  H01L2224/376 ,  H01L2224/4007 ,  H01L2224/40227 ,  H01L2224/40499 ,  H01L2224/756 ,  H01L2224/75703 ,  H01L2224/776 ,  H01L2224/77703 ,  H01L2224/821 ,  H01L2224/82101 ,  H01L2224/83007 ,  H01L2224/831 ,  H01L2224/834 ,  H01L2224/83411 ,  H01L2224/83424 ,  H01L2224/83439 ,  H01L2224/83444 ,  H01L2224/83447 ,  H01L2224/83455 ,  H01L2224/83466 ,  H01L2224/8349 ,  H01L2224/83511 ,  H01L2224/83524 ,  H01L2224/83539 ,  H01L2224/83544 ,  H01L2224/83547 ,  H01L2224/83555 ,  H01L2224/83566 ,  H01L2224/8359 ,  H01L2224/836 ,  H01L2224/83695 ,  H01L2224/8385 ,  H01L2224/83907 ,  H01L2224/84007 ,  H01L2224/841 ,  H01L2224/8485 ,  H01L2224/8492 ,  H01L2224/84951 ,  H01L2224/9201 ,  H01L2224/9205 ,  H01L2224/9221 ,  H01L2224/97 ,  H01L2924/13055 ,  H01L2924/181 ,  H05K3/424 ,  H01L2924/00012 ,  H05K3/4661 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01028 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/0105 ,  H01L2224/83 ,  H01L2224/84 ,  H01L2224/82 ,  H01L2924/01014

摘要： The invention relates to a method for electrically contacting a component (10) (for example a power component and/or a (semiconductor) component having at least one transistor, preferably an IGBT (insulated-gate bipolar transistor)) having at least one contact (40, 50), at least one open-pored contact piece (60, 70) is galvanically (electrochemically or free of external current) connected to at least one contact (40, 50). In this way, a component module is achieved. The contact (40, 50) is preferably a flat part or has a contact surface, the largest planar extent thereof being greater than an extension of the contact (40, 50) perpendicular to said contact surface. The temperature of the galvanic connection is at most 100 °C, preferably at most 60 °C, advantageously at most 20 °C and ideally at most 5 °C and/or deviates from the operating temperature of the component by at most 50 °C, preferably by at most 20 °C, in particular by at most 10 °C and ideally by at most 5 °C, preferably by at most 2 °C. The component (10) can be contacted by means of the contact piece (60, 70) with a further component, a current conductor and/or a substrate (90). Preferably, a component (10) having two contacts (40, 50) on opposite sides of the component (10) is used, wherein at least one open-pored contact piece (60, 70) is galvanically connected to each contact (40, 50).

公开(公告)号：EP2731130A1

公开(公告)日：2014-05-14

申请号：EP12192281.9

申请日：2012-11-12

申请人： NXP B.V.

发明人： Weinschenk, Christian

IPC分类号： H01L23/31 ,  H01L21/56

CPC分类号： H01L23/49 ,  H01L21/56 ,  H01L23/3121 ,  H01L23/315 ,  H01L24/42 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： The invention refers to method for packaging an integrated circuit (IC) comprising steps of:
- attaching at least one die on a substrate;
- attaching bond-wires from the die(s) to package terminal pads;
- mold or dispense a thermo-degradable material on the substrate, die(s) and bond-wires;
- mold an encapsulant material;
- decompose the thermo-degradable materials by temperature treatment.

摘要翻译： 本发明涉及一种用于封装集成电路（IC）的方法，包括以下步骤： - 将至少一个管芯附着在衬底上; - 将粘合线从模具附接到封装端子焊盘; - 在基底，模具和接合线上模制或分配热可降解材料; - 模塑密封材料; - 通过温度处理分解热降解材料。