摘要:
A receiver according to one aspect comprises a latch configured to sample a data signal according to a sampling clock signal, and a plurality of offset-compensation segments, wherein each of the segments is coupled to an internal node of the latch. Each of the segments comprises a compensation transistor, and a step-adjustment transistor coupled in series with the compensation transistor. The receiver further comprises an offset controller configured to selectively turn on one or more of the compensations transistors to reduce an offset voltage of the latch, and a bias circuit configured to apply a bias voltage to a gate of each of one or more of the step-adjustment transistors.
摘要:
The present invention provides a control circuit (1 20) to stabilize an output power of a power amplifier (110). The control circuit (120) comprises a voltage clamping loop (1 30), a current clamping loop (140) and a loop (1 50) for reducing power variation under VSWR, where the voltage clamping loop (1 30) is used to clamp an output voltage of the power amplifier (110) within a defined voltage range, the current clamping loop (140) is used to clamp a current of the power amplifier (110) within a defined current range, and the loop (1 50) for reducing power variation under VSWR is implemented by an impedance detector (1 50) to compensate the output power under VSWR variation.
摘要:
A current controlling device (100) includes: a first resistive circuit (102) arranged to selectively conduct a first current (I1) to a first output terminal (No1) from a first input terminal (Ni1); and a second resistive circuit (104) arranged to selectively conduct a second current (12) to a second output terminal (No2) from the first input terminal (Ni1); wherein when the first resistive circuit (102) conducts the first current (I1) to the first output terminal (No1) and when the second resistive circuit (104) does not conduct the second current (I2) to the second output terminal (No2), the first input terminal (Ni1) has a first input impedance; when the first resistive circuit (102) does not conduct the first current (I1) to the first output terminal (No2) and when the second resistive circuit (104) conducts the second current (I2) to the second output terminal (No2), the first input terminal (Ni1) has a second input impedance substantially equal to the first input impedance.
摘要:
An operational amplifier comprising two cascaded differential stages and suitable for an RC filter An operational amplifier with a differential input and a differential output comprises two cascaded differential stages 4 and 6 of relatively low gain, a dominant pole compensation capacitor being placed between the output nodes of the second stage 6. The propagation delay and power consumption may be low. The output common-mode voltage of the first or second stage may be controlled by use of a local replica circuit adjusting the current sources 12, 30. The amplifier may be used in a leapfrog active RC filter (figure 2).
摘要:
A radio frequency (RF) power amplifier circuit with spur cancellation for GSM/GPRS/EDGE transceivers is disclosed. There is a power amplifier with an RF input, an RF output, and a voltage supply input. Additionally, there is an adjustable DC-DC converter with an input connected to a battery, an output connected to the voltage supply input of the power amplifier with a DC supply voltage signal generated thereby. A spur compensator generates an error control signal responsive to spurs in the DC supply voltage signal. The error control signal is applied to the RF input of the power amplifier.
摘要:
A current controlling device (100) includes: a first resistive circuit (102) arranged to selectively conduct a first current (I1) to a first output terminal (No1) from a first input terminal (Ni1); and a second resistive circuit (104) arranged to selectively conduct a second current (12) to a second output terminal (No2) from the first input terminal (Ni1); wherein when the first resistive circuit (102) conducts the first current (I1) to the first output terminal (No1) and when the second resistive circuit (104) does not conduct the second current (I2) to the second output terminal (No2), the first input terminal (Ni1) has a first input impedance; when the first resistive circuit (102) does not conduct the first current (I1) to the first output terminal (No2) and when the second resistive circuit (104) conducts the second current (I2) to the second output terminal (No2), the first input terminal (Ni1) has a second input impedance substantially equal to the first input impedance.
摘要:
Ausgangspufferverstärker mit einer Endstufe (1, 2, 3, 4, 7, 8) für kleine Ausgangsleistungen und einer Endstufe (9, 10, 13, 14, 15, 16) für große Ausgangsleistungen, deren Ausgänge miteinander verbunden sind, und mit einer Regelstufe (12), die der Endstufe (1, 2, 3, 4, 7, 8) für kleine Ausgangsleistungen vorgeschaltet ist und deren einer Eingang durch ein einem Eingangssignal der Endstufe (9, 10, 13, 14, 15, 16) für große Ausgangsleistungen proportionales Signal und deren anderer Eingang durch ein einem Ausgangssignal der Endstufe (1, 2, 3, 4, 7, 8) für kleine Ausgangsleistungen proportionales Signal angesteuert wird.
摘要:
In one embodiment, the present disclosure includes a circuit comprising a first power amplifier stage having an input to receive an input signal, an output coupled to an output node, the first power amplifier stage receiving a time-varying power supply voltage. The circuit further includes a second power amplifier stage configured in parallel with the first power amplifier stage having an input to receive the input signal, an output coupled to the output node, the second power amplifier stage receiving the time-varying power supply voltage. A first gain of the first power amplifier stage decreases when the power supply voltage is in a first low voltage range, and a second gain of the second power amplifier stage compensates for the decreasing gain of the first power amplifier stage in the first low voltage range.