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    HIGH-SWING OPERATIONAL AMPLIFIER OUTPUT STAGE USING ADAPTIVE BIASING
    1.
    发明公开
    HIGH-SWING OPERATIONAL AMPLIFIER OUTPUT STAGE USING ADAPTIVE BIASING 审中-公开
    大信号摆幅运算放大器输出级使用自适应偏置

    公开(公告)号：EP2193603A1

    公开(公告)日：2010-06-09

    申请号：EP08828033.4

    申请日：2008-08-21

    申请人： QUALCOMM Incorporated

    发明人： DABAG, Hayg ,  SEO, Dongwon ,  MISHRA, Manu

    IPC分类号： H03F3/30 ,  H03F3/45 ,  H03F1/52

    CPC分类号： H03F3/45192 ,  H03F1/52 ,  H03F1/523 ,  H03F3/303 ,  H03F2203/30015 ,  H03F2203/30084 ,  H03F2203/30117 ,  H03F2203/45244 ,  H03F2203/45626 ,  H03F2203/45732

    摘要： An output stage (123) includes two transistors (T3, T4) (switching transistor, and biasing transistor) coupled in series in a pullup current path between a VDDA node and an output node, (120) and also includes two transistors (Tl, T2) (switching transistor and biasing transistor) coupled in series in a pulldown current path between the output node (121) and a ground node. Providing the biasing transistors (T2,T4) reduces the maximum voltage dropped across the transistors, thereby allowing the transistors to have lower breakdown voltages than VDDA. An adaptive biasing circuit (26) adjusts the gate voltage on a biasing transistor (T2,T4) based on the output node (121) voltage. If the output voltage is in a midrange, then the gate voltage is set farther away from a rail voltage in order to reduce voltage stress. If the output voltage is in a range closer to the rail voltage, then the gate voltage is set closer to the rail voltage, thereby facilitating rail-to-rail output voltage swings.

    Differential amplifier with common-mode stability enhancement
    2.
    发明公开
    Differential amplifier with common-mode stability enhancement 失效
    Differentialzverstärkermit verbesserterGleichtaktstabilität。

    公开(公告)号：EP0554743A1

    公开(公告)日：1993-08-11

    申请号：EP93101067.2

    申请日：1993-01-25

    申请人： MOTOROLA, INC.

    发明人： Brooks, Todd L. ,  Rybicki, Mathew A.

    IPC分类号： H03F3/45

    CPC分类号： H03F3/45192 ,  H03F3/45183 ,  H03F3/4565 ,  H03F2203/30084 ,  H03F2203/30117 ,  H03F2203/45008 ,  H03F2203/45074 ,  H03F2203/45082 ,  H03F2203/45221 ,  H03F2203/45318 ,  H03F2203/45418 ,  H03F2203/45424 ,  H03F2203/45466 ,  H03F2203/45471 ,  H03F2203/45631 ,  H03F2203/45644

    摘要： A differential amplifier (60, 60') enhances common-mode stability by making two nodes (86, 87) of a first stage low common-mode impedance nodes and thus shifting a common-mode dominant pole from the two nodes (86, 87). The first stage includes an input portion (80, 80') and a differential load (110, 110'). The input portion (80, 80') provides first and second currents respectively to the differential load (110, 110') in response to a differential input voltage. The first and second currents have a differential component and a common-mode component. The differential load (110, 110') converts the differential and common-mode components of the first and second currents into differential and common-mode voltages, respectively, and provides a high impedance to the differential component and a low impedance to the common-mode component.

    摘要翻译： 差分放大器（60,60'）通过制造第一级低共模阻抗节点的两个节点（86,87）并因此从两个节点（86,87）移动共模主导极来增强共模稳定性 ）。 第一级包括输入部分（80,80'）和差分负载（110,110'）。 输入部分（80,80'）响应于差分输入电压分别向差分负载（110,110'）提供第一和第二电流。 第一和第二电流具有差分分量和共模分量。 差分负载（110,110'）分别将第一和第二电流的差分和共模分量转换成差模和共模电压，并且向差动分量提供高阻抗， 模式组件。

    Switched amplifier circuit arrangement and method for switched amplification
    5.
    发明授权
    Switched amplifier circuit arrangement and method for switched amplification 有权
    用于切换增益放大电路和方法

    公开(公告)号：EP2293434B1

    公开(公告)日：2013-04-03

    申请号：EP09011069.3

    申请日：2009-08-28

    申请人： ams AG

    发明人： Yan, Weixun

    IPC分类号： H03F1/30

    CPC分类号： H03F1/303 ,  H03F1/308 ,  H03F3/187 ,  H03F3/45179 ,  H03F2203/30084 ,  H03F2203/30117

    摘要： A switched amplifier circuit arrangement comprises a main amplifier (Amp) having an input terminal (In) and an output terminal (Out) and a regulating amplifier (rAmp) to set an input and an output operating point of the main amplifier (Amp). The regulating amplifier (rAmp) exhibits an auxiliary amplifier (A) having a first input terminal coupled to a reference level (Vref), a second input terminal (Ain) coupled to the output terminal (Out), and an output terminal (Aout) which is connected via a first switch (S1) to the input terminal (In). Moreover, the switched amplifier circuit arrangement comprises a cancellation capacitor (Cc) coupled to the input terminal (In), a second switch (S2) which is coupled between the output terminal (Out) and the cancellation capacitor (Cc) at a first circuit node (n1), and a third switch (S3) connected between the circuit node (n1) and the reference level (Vref).

    Amplifying circuit
    6.
    发明公开
    Amplifying circuit 有权
    放大电路

    公开(公告)号：EP2424106A3

    公开(公告)日：2012-07-04

    申请号：EP11173792.0

    申请日：2011-07-13

    申请人： Onkyo Corporation

    发明人： Kawaguchi, Tsuyoshi ,  Kitagawa, Norimasa ,  Sekiya, Mamoru ,  Shimasaki, Naofumi

    IPC分类号： H03F3/30 ,  H03F3/343 ,  H03F1/34 ,  H03F1/52

    CPC分类号： H03F3/3076 ,  H03F1/34 ,  H03F1/52 ,  H03F3/3066 ,  H03F3/3435 ,  H03F2203/30031 ,  H03F2203/30084 ,  H03F2203/30117

    摘要： An amplifying circuit comprises: a first transistor, a second transistor, a third transistor and a fourth transistor provided in an input stage; and a first bias circuit. The input signal is input into a control terminal of the first transistor and a control terminal of the second transistor, a first terminal of the first transistor is connected to a first terminal of the third transistor, a first terminal of the second transistor is connected to a first terminal of the fourth transistor, a second terminal of the first transistor is connected to a first potential, a second terminal of the second transistor is connected to a second potential that is equal to or different from the first potential, a second terminal of the third transistor is connected to a third potential, a second terminal of the fourth transistor is connected to a fourth potential, the first bias circuit is connected between a control terminal of the third transistor and a control terminal of the fourth transistor.

    摘要翻译： 放大电路包括：设置在输入级中的第一晶体管，第二晶体管，第三晶体管和第四晶体管; 和第一偏置电路。 输入信号被输入到第一晶体管的控制端子和第二晶体管的控制端子，第一晶体管的第一端子连接到第三晶体管的第一端子，第二晶体管的第一端子连接到第一晶体管的第二端子 第四晶体管的第一端子，第一晶体管的第二端子连接到第一电位，第二晶体管的第二端子连接到与第一电位相等或不同的第二电位，第二晶体管的第二端子 第三晶体管连接到第三电位，第四晶体管的第二端连接到第四电位，第一偏置电路连接在第三晶体管的控制端和第四晶体管的控制端之间。

    Amplifying circuit
    7.
    发明公开
    Amplifying circuit 有权
    Verstärkungsschaltung

    公开(公告)号：EP2424106A2

    公开(公告)日：2012-02-29

    申请号：EP11173792.0

    申请日：2011-07-13

    申请人： Onkyo Corporation

    发明人： Kawaguchi, Tsuyoshi ,  Kitagawa, Norimasa ,  Sekiya, Mamoru ,  Shimasaki, Naofumi

    IPC分类号： H03F3/30

    CPC分类号： H03F3/3076 ,  H03F1/34 ,  H03F1/52 ,  H03F3/3066 ,  H03F3/3435 ,  H03F2203/30031 ,  H03F2203/30084 ,  H03F2203/30117

    摘要： An amplifying circuit comprises: a first transistor, a second transistor, a third transistor and a fourth transistor provided in an input stage; and a first bias circuit. The input signal is input into a control terminal of the first transistor and a control terminal of the second transistor, a first terminal of the first transistor is connected to a first terminal of the third transistor, a first terminal of the second transistor is connected to a first terminal of the fourth transistor, a second terminal of the first transistor is connected to a first potential, a second terminal of the second transistor is connected to a second potential that is equal to or different from the first potential, a second terminal of the third transistor is connected to a third potential, a second terminal of the fourth transistor is connected to a fourth potential, the first bias circuit is connected between a control terminal of the third transistor and a control terminal of the fourth transistor.

    摘要翻译： 放大电路包括：设置在输入级中的第一晶体管，第二晶体管，第三晶体管和第四晶体管; 和第一偏置电路。 输入信号被输入到第一晶体管的控制端子和第二晶体管的控制端子，第一晶体管的第一端子连接到第三晶体管的第一端子，第二晶体管的第一端子连接到 第四晶体管的第一端子，第一晶体管的第二端子连接到第一电位，第二晶体管的第二端子连接到等于或不同于第一电位的第二电位，第二端子的第二端子 第三晶体管连接到第三电位，第四晶体管的第二端连接到第四电位，第一偏置电路连接在第三晶体管的控制端和第四晶体管的控制端之间。

    Amplifying circuit
    10.
    发明授权
    Amplifying circuit 有权

    公开(公告)号：EP2424106B1

    公开(公告)日：2018-06-20

    申请号：EP11173792.0

    申请日：2011-07-13

    申请人： Onkyo Corporation

    发明人： Kawaguchi, Tsuyoshi ,  Kitagawa, Norimasa ,  Sekiya, Mamoru ,  Shimasaki, Naofumi

    IPC分类号： H03F3/30 ,  H03F3/343 ,  H03F1/34 ,  H03F1/52

    CPC分类号： H03F3/3076 ,  H03F1/34 ,  H03F1/52 ,  H03F3/3066 ,  H03F3/3435 ,  H03F2203/30031 ,  H03F2203/30084 ,  H03F2203/30117

    摘要： An amplifying circuit comprises: a first transistor, a second transistor, a third transistor and a fourth transistor provided in an input stage; and a first bias circuit. The input signal is input into a control terminal of the first transistor and a control terminal of the second transistor, a first terminal of the first transistor is connected to a first terminal of the third transistor, a first terminal of the second transistor is connected to a first terminal of the fourth transistor, a second terminal of the first transistor is connected to a first potential, a second terminal of the second transistor is connected to a second potential that is equal to or different from the first potential, a second terminal of the third transistor is connected to a third potential, a second terminal of the fourth transistor is connected to a fourth potential, the first bias circuit is connected between a control terminal of the third transistor and a control terminal of the fourth transistor.