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公开(公告)号：EP3180861A1
公开(公告)日：2017-06-21
申请号：EP15741627.2
申请日：2015-06-11
申请人： Raytheon Company
CPC分类号： H03M1/128 , G01R23/16 , H03M1/1265 , H04B1/16
摘要： A method includes generating a sampling signal having a non-uniform sampling interval and sampling a received signal with an analog-to-digital converter (ADC) using the sampling signal. The method also includes mapping the sampled received signal onto a frequency grid of sinusoids, where each sinusoid has a signal amplitude and a signal phase. The method further includes estimating the signal amplitude and the signal phase for each sinusoid in the frequency grid. In addition, the method includes computing an average background power level and detecting signals with power higher than the average background power level. The non-uniform sampling interval varies predictably.
摘要翻译： 一种方法包括：生成具有非均匀采样间隔的采样信号;以及使用采样信号，利用模数转换器（ADC）对接收到的信号进行采样。 该方法还包括将采样的接收信号映射到正弦曲线的频率网格上，其中每个正弦曲线具有信号幅度和信号相位。 该方法还包括估计频率网格中每个正弦曲线的信号幅度和信号相位。 另外，该方法包括计算平均背景功率电平并检测功率高于平均背景功率电平的信号。 非均匀采样间隔可预测地变化。
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公开(公告)号：EP3095194A1
公开(公告)日：2016-11-23
申请号：EP14879162.7
申请日：2014-12-03
CPC分类号： H03M1/1245 , H03M1/0624 , H03M1/1009 , H03M1/1265 , H03M1/38 , H03M1/46
摘要： A cognitive signal converter connectable to an analog signal source via an analog signal input port and adapted to produce a digital output signal based on an analog input signal received via the analog signal input port is disclosed. The cognitive signal converter comprises an analog-to-digital converter and a cognitive network. The analog-to-digital converter is adapted to produce a digital converted signal based on the analog input signal, a sample clock signal and a process clock signal by sampling the analog input signal in accordance with the sample clock signal and quantizing each analog input signal sample, wherein the quantizing process is operated by the process clock signal. The cognitive network is adapted to receive the digital converted signal of the analog-to-digital converter, control at least one of the sample clock signal and the process clock signal based on the received digital converted signal and one or more characteristics of the analog signal source, and produce the digital output signal based on the received digital converted signal. Corresponding integrated circuit, electronic device and method are also disclosed.
摘要翻译： 公开了一种通过模拟信号输入端口连接到模拟信号源并适于产生基于经由模拟信号输入端口接收的模拟输入信号的数字输出信号的认知信号转换器。 认知信号转换器包括模数转换器和认知网络。 模拟 - 数字转换器适于基于模拟输入信号，采样时钟信号和处理时钟信号，通过根据采样时钟信号对模拟输入信号进行采样并量化每个模拟输入信号来产生数字转换信号 样本，其中量化处理由处理时钟信号操作。 认知网络适于接收模拟 - 数字转换器的数字转换信号，基于接收的数字转换信号和模拟信号的一个或多个特性来控制采样时钟信号和处理时钟信号中的至少一个 源，并且基于接收到的数字转换信号产生数字输出信号。 还公开了相应的集成电路，电子设备和方法。
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3.发明公开SAMPLING CIRCUIT, A/D CONVERTER, D/A CONVERTER, CODEC 审中-公开ABTASTSCHALTUNG，A / D-WANDLER，D / A-WANDLER UND CODEC
公开(公告)号：EP2642666A1
公开(公告)日：2013-09-25
申请号：EP12842682.2
申请日：2012-12-27
IPC分类号： H03M1/08
CPC分类号： H03M1/1245 , H03M1/0656 , H03M1/12 , H03M1/1265 , H03M1/66
摘要： An A/D converter comprising: a sampling circuit (140) including a continuous section (130a), a sampling and holding section (130b) for intermittently sampling an input signal based on an analog signal input from the continuous section (130a) to hold and transfer the sampled signal, and a digital section (130c) for outputting a signal transferred from the sampling and holding section (130b) as a digital signal; and a control circuit (139) for supplying a clock signal (φ1) in which jitter is not added to the continuous section (130a) and supplying a clock signal (φ2') in which the jitter is added to the sampling and holding section (130b).
摘要翻译： 一种A / D转换器，包括：采样电路（140），包括连续部分（130a），采样和保持部分（130b），用于基于从连续部分（130a）输入的模拟信号来间歇地采样输入信号，以保持 并传送采样信号;以及数字部分（130c），用于输出从采样和保持部分（130b）传送的信号作为数字信号; 以及控制电路（139），用于向不连续部分（130a）提供不添加抖动的时钟信号（Æ1），并将提供抖动的时钟信号（Æ2'）提供给采样保持部分（Æ2'） 130B）。
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公开(公告)号：EP3104529A1
公开(公告)日：2016-12-14
申请号：EP16305701.1
申请日：2016-06-10
申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES , The Trustees of Columbia University in the City of New York
CPC分类号： H03M3/368 , H03M1/0626 , H03M1/125 , H03M1/1265 , H04B1/10 , H04B2001/1063
摘要： The invention concerns an analog to digital conversion and filtering circuit comprising: an input for receiving an analog input signal (x(t)); an asynchronous continuous-time analog to digital converter (412) adapted to generate, based on the analog input signal (x(t)), a digital continuous-time signal (y(t)); a feedback path comprising a digital continuous-time filter (414) adapted to generate a filtered signal (f(t)) to be combined with the analog input signal (x(t)), the digital continuous-time filter being adapted to generate the filtered signal (f(t)) by: filtering out at least one first frequency range of the digital continuous-time signal (y(t)); and amplifying at least one second frequency range of the digital continuous-time signal (y(t)).
摘要翻译： 本发明涉及一种模数转换和滤波电路，包括：用于接收模拟输入信号（x（t））的输入端; 一种适于基于模拟输入信号（x（t））生成数字连续时间信号（y（t））的异步连续时间模数转换器（412）; 反馈路径，包括适于产生要与模拟输入信号（x（t））组合的滤波信号（f（t））的数字连续时间滤波器（414），数字连续时间滤波器适于产生 滤波后的信号（f（t））：滤除数字连续时间信号（y（t））的至少一个第一频率范围; 以及放大数字连续时间信号（y（t））的至少一个第二频率范围。
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5.发明公开
公开(公告)号：EP2681846A1
公开(公告)日：2014-01-08
申请号：EP12716115.6
申请日：2012-02-27
发明人： SU, David, Kuochieh
CPC分类号： H03M1/1265 , H03M1/48
摘要： A data converter circuit includes a non-uniform sampling circuit and a resampler circuit. The non-uniform sampling circuit includes a sampling voltage-controlled oscillator (VCO) having an input to receive an analog data signal and having an output to generate a quantized data signal, wherein the quantized data signal comprises a plurality of non-uniform transition intervals indicative of data contained in the analog data signal. The resampling circuit has an input to receive the quantized data signal and is configured to reconstruct the data from the quantized data signal. For some embodiments, the data converter can also include a PLL that includes a feedback VCO having matched components with the sampling VCO.
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公开(公告)号：EP1775837B1
公开(公告)日：2013-09-11
申请号：EP05765640.7
申请日：2005-07-14
CPC分类号： H03M1/661 , H03M1/1265 , H03M7/30
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7.发明公开DISCRETE SIGNAL PROCESSING DEVICE AND PROCESSING METHOD 有权EINRICHTUNG UND VERARBEITUNGSVERFAHRENFÜRDISKRETE SIGNALVERARBEITUNG
公开(公告)号：EP1775837A1
公开(公告)日：2007-04-18
申请号：EP05765640.7
申请日：2005-07-14
CPC分类号： H03M1/661 , H03M1/1265 , H03M7/30
摘要： A signal processing device and a signal processing method are provided which can reproduce a smooth signal in the reproduction of a discrete signal having a non-uniform sample point interval. The device includes a coefficient calculation unit 4 that inputs a sample point signal E2 representative of the time of a sample point of a discrete signal E1 having a non-uniform sample point interval to obtain a coefficient of a sampling function corresponding to the discrete signal, and a reproduction signal calculation unit 5 that obtains a continuous reproduction signal E3 by calculating and outputting a function value within the sample point interval from the discrete signal and the value of the coefficient outputted by the coefficient calculation unit.
摘要翻译： 提供信号处理装置和信号处理方法，其可以在具有不均匀采样点间隔的离散信号的再现中再现平滑信号。 该装置包括系数计算单元4，其输入表示具有不均匀采样点间隔的离散信号E1的采样点的时间的采样点信号E2，以获得对应于离散信号的采样函数的系数， 以及再现信号计算单元5，其通过从离散信号计算并输出采样点间隔内的函数值和由系数计算单元输出的系数值来获得连续再现信号E3。
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公开(公告)号：EP3357163A1
公开(公告)日：2018-08-08
申请号：EP16774812.8
申请日：2016-09-22
申请人： Google LLC
CPC分类号： H03M1/0639 , H03M1/1265
摘要： A radio frequency receiver includes an antenna that receives an analog signal comprising modulated encoded information. An analog signal generator generates a supplemental analog signal characterized by an amplitude sufficient to trigger a voltage threshold in a non-uniform sampling analog-to-digital converter. A mixer mixes the received signal and the supplemental signal. A non-uniform sampling analog-to-digital converter receives the mixed signal and produces a series of non-uniformly sampled {amplitude, time} tuples representing the mixed signal. The converter removes the supplemental signal from the series of {amplitude, time} tuples to produce a series of non-uniformly sampled {amplitude, time} tuples representative of the mixed signal without the supplemental signal. The converter interpolates the series of non-uniformly sampled {amplitude, time} tuples to form a series of samples periodic in time representative of the analog input signal. A digital signal processor (DSP) demodulates the interpolated series and decode the digital information from the demodulated series.
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公开(公告)号：EP3353895A1
公开(公告)日：2018-08-01
申请号：EP16774813.6
申请日：2016-09-22
申请人： Google LLC
CPC分类号： H03M1/0639 , H03M1/1265
摘要： Analog-to-digital conversion is performed on a received an analog input signal. A supplemental analog signal is generated. The supplemental analog signal is characterized by an amplitude sufficient to trigger each voltage threshold in a non-uniform sampling analog- to-digital converter. The received analog input signal and the generated supplemental signal are mixed. The non-uniform sampling analog-to-digital converter converts the mixed analog signal, producing a series of {amplitude, time} tuples representative of the mixed signal. The series of {amplitude, time} tuples are interpolated to form a series of samples periodic in time representative of the mixed signal. The supplemental signal is removed from the interpolated series.
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公开(公告)号：EP2553818B1
公开(公告)日：2016-11-23
申请号：EP11713582.2
申请日：2011-03-29
发明人： CZOMPO, Joseph
IPC分类号： H03M1/12
CPC分类号： H03M1/1265 , H03M1/1225
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