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    RECONFIGURABLE TURBO INTERLEAVER FOR MULTIPLE STANDARDS
    1.
    发明公开
    RECONFIGURABLE TURBO INTERLEAVER FOR MULTIPLE STANDARDS 审中-公开
    TURBO可重构交织多重标准

    公开(公告)号：EP2297859A1

    公开(公告)日：2011-03-23

    申请号：EP09762139.5

    申请日：2009-06-09

    申请人： NXP B.V.

    发明人： DILONARDO, Angelo Raffaele ,  ENGIN, Nur

    IPC分类号： H03M13/27 ,  H03M13/29

    CPC分类号： H03M13/2775 ,  H03M13/2739 ,  H03M13/2753 ,  H03M13/2764 ,  H03M13/2957 ,  H03M13/6519 ,  H03M13/6525 ,  H03M13/6544

    摘要： A data processing system, a turbo decoding system, an address generator and a method of reconfiguring a turbo decoding method is provided. The data processing system (101) comprises the turbo decoding system (100). The turbo decoding system (100) comprises electronic circuits. The electronic circuits comprises: a memory (108), the address generator (102), and a Soft Input Soft Output decoder (106). The address generator (102) is operative to produce a sequence of addresses according to an interleaving scheme. The address generator can support multiple interleaving schemes. The address generator (102) is operative to receive reconfiguration information. The address generator (102) is operative to reconfigure during operational use the interleaving scheme in dependency on the reconfiguration information.

    METHOD AND APPARATUS FOR ENCODING AND DECODING DATA
    2.
    发明公开
    METHOD AND APPARATUS FOR ENCODING AND DECODING DATA 审中-公开
    方法和设备数据编码和解码

    公开(公告)号：EP2119017A1

    公开(公告)日：2009-11-18

    申请号：EP08729736.2

    申请日：2008-02-13

    申请人： Motorola, Inc.

    发明人： NIMBALKER, Ajit ,  BLANKENSHIP, Yufei, W. ,  CLASSON, Brian, K.

    IPC分类号： H03M13/27 ,  H03M13/29

    CPC分类号： H03M13/2957 ,  H03M13/2739 ,  H03M13/2753 ,  H03M13/2775 ,  H03M13/2789 ,  H03M13/2903 ,  H03M13/6525

    摘要： A method and apparatus for turbo encoding with a contention-free interleaver is provided herein. During operation an input block of size K' is received. The original input block and the interleaved input block are encoded to obtain a codeword block, wherein the original input block is interleaved using an interleaver of size K' and a permutation π(i)= ( ƒ1 x i + ƒ2 x i2) mod K', where O ≤ i ≤ K'-1 is the sequential index of the symbol positions after interleaving, π(i) is the symbol index before interleaving corresponding to position i, K' is the interleaver size in symbols, and/i and /2 are the factors defining the interleaver. The values of K', ƒ1, ƒ2 are taken from at least one row of a table. The codeword block is transmitted through the channel.

    Address generation for contention-free memory mappings of turbo codes with ARP (almost regular permutation) interleaves
    4.
    发明公开
    Address generation for contention-free memory mappings of turbo codes with ARP (almost regular permutation) interleaves 审中-公开
    Adressgenerierungfürkonkurrenzfreie Speicherabbildungen von Turbocodes mit ARP-Verschachtelungen

    公开(公告)号：EP1942578A1

    公开(公告)日：2008-07-09

    申请号：EP07021040.6

    申请日：2007-10-26

    申请人： Broadcom Corporation

    发明人： Lee, Tak K. ,  Shen, Ba-Zhong

    IPC分类号： H03M13/27 ,  H03M13/29

    CPC分类号： H03M13/2775 ,  H03M13/2753 ,  H03M13/276 ,  H03M13/2957 ,  H03M13/6566

    摘要： Address generation for contention-free memory mappings of turbo codes with ARP (almost regular permutation) interleaves. A novel means is presented by which anticipatory address generation is employed using an index function (F), that is based on an address mapping (A), which corresponds to an interleave inverse order of decoding processing (π -1 ). In accordance with parallel turbo decoding processing, instead of performing the natural order phase decoding processing by accessing data elements from memory bank locations sequentially, the accessing of addresses is performed based on the index function (F), that is based on an mapping and the interleave (π) employed within the turbo coding. In other words, the accessing data elements from memory bank locations is not sequential for natural order phase decoding processing. The index function (F) also allows for the interleave (π) order phase decoding processing to be performed by accessing data elements from memory bank locations sequentially.

    摘要翻译： 具有ARP（几乎规则排列）交织的turbo码的无竞争内存映射的地址生成。 提出了一种新颖的方法，其中使用基于地址映射（A）的索引函数（F）来采用预期地址生成，其对应于解码处理（-1）的交织逆序。 根据并行turbo解码处理，代替通过依次从存储体单元访问数据元素来执行自然次序相位解码处理，基于索引函数（F），基于映射执行地址的访问，并且 在turbo编码中使用交织（À）。 换句话说，来自存储体位置的访问数据元素对于自然顺序相位解码处理不是顺序的。 索引函数（F）还允许通过从存储体位置顺序访问数据元素来进行交织（À）阶相位解码处理。

    CONCEPTION DE L'ENTRELACEUR POUR DES CODES TURBO EN FONCTION DU MOTIF DE POINÇONNAGE
    5.
    发明公开
    CONCEPTION DE L'ENTRELACEUR POUR DES CODES TURBO EN FONCTION DU MOTIF DE POINÇONNAGE 审中-公开
    基于冲切模式的Turbo编码交互设计

    公开(公告)号：EP3311495A1

    公开(公告)日：2018-04-25

    申请号：EP16729939.5

    申请日：2016-06-20

    申请人： Orange ,  Institut Télécom - Télécom Bretagne

    发明人： GARZON BOHORQUEZ, Ronald Edicson ,  ABDEL NOUR, Charbel ,  DOUILLARD, Catherine

    IPC分类号： H03M13/27

    CPC分类号： H03M13/2771 ,  H03M13/2753 ,  H03M13/6362

    摘要： The present invention relates to a method for coding a digital input message, having K information symbols, using a turbo encoder forming a turbo code, the turbo encoder comprising an interleaver and first and second encoders (C1, C2) encoding according to at least one elementary code, and delivering information symbols and redundancy symbols. According to the invention, a puncturing of symbols delivered by the turbo encoder being carried out according to at least one periodic puncturing pattern of length N, defining the puncturing period N, said interleaver distributes the information symbols of said input message in Q input message layers interleaved according to an interleaving function defined from said at least one puncturing pattern, according to the relationship π(i) = Pi + S(i mod Q) mod K = Pi + (T
    l + A
    l Q) mod K.