摘要:
A semiconductor device, comprising: a semiconductor substrate (30); a nonvolatile memory cell (47) including a first MOS transistor having a first gate formed on the semiconductor substrate, the first gate being a layered gate structure having a first gate insulating film (32), a first gate electrode film (33), a second gate insulating film (34), a second gate electrode film (44), and a source and a drain (46) formed in the semiconductor substrate to interpose a surface region of the semiconductor substrate beneath the first gate; and a logic circuit including a plurality of second MOS transistors, each of the second MOS transistors having a second gate formed on the semiconductor substrate, the second gate being a gate structure having a third gate insulating film and a second gate electrode film, and a source and a drain formed in the semiconductor substrate to interpose a surface region of the semiconductor substrate beneath the second gate, the plurality of second MOS transistors including at least a second MOS transistor having a third gate insulating film of a first thickness (38), a second MOS transistor having a third gate insulating film of a second thickness (40) and a second MOS transistor having a third gate insulating film of a third thickness (42); wherein the first thickness is thicker than the second thickness and the second thickness is thicker than the third thickness, and a thickness of the second gate insulating film is thicker than the second thickness and thinner than the first thickness.
摘要:
A method for manufacturing a semiconductor device includes providing a substrate structure having an active region, a gate insulating layer, a charge storage layer, a gate dielectric layer, and a gate electrode layer sequentially formed on the active region. The method also includes forming a patterned metal layer on the substrate structure, removing a respective portion of the gate electrode layer, the gate dielectric layer, the charge storage layer using the patterned metal gate electrode layer as a mask to form multiple gate structures separated from each other by a space. The gate structures each include a stack containing a second portion of the charge storage layer, the gate dielectric layer, the gate electrode layer, and one of the gate lines. The method further includes forming an interlayer dielectric layer on a surface of the gate structures stretching over the space while forming an air gap in the space.