公开(公告)号：EP0484987A2

公开(公告)日：1992-05-13

申请号：EP91121805.5

申请日：1988-01-21

申请人： HOSIDEN CORPORATION

发明人： Ukai, Yasuhiro ,  Aoki, Shigeo

IPC分类号： H01L29/784 ,  H01L29/163 ,  H01L29/161 ,  H01L29/62

CPC分类号： G02F1/1368 ,  H01L29/154 ,  H01L29/1604 ,  H01L29/432 ,  H01L29/7782 ,  H01L29/78684 ,  H01L29/78687 ,  H01L31/03765 ,  Y02E10/548

摘要： A thin film transistor having an active layer (24) formed between source and drain electrodes (14,15), a gate insulating film (25) formed in contact with the active layer (24) and a gate electrode (18) formed in contact with the gate insulating film (25), said active layer (24) being a multilayer structure of well layers made of hydrogenated amorphous silicon and barrier layers made of hydrogenated amorphous silicon carbide. The gate insulating film (25) can further be made of an amorphous silicon carbide layer having a carbon content greater than the carbon content of the active layer (24).

公开(公告)号：EP0484987A3

公开(公告)日：1992-08-05

申请号：EP91121805.5

申请日：1988-01-21

申请人： HOSIDEN CORPORATION

发明人： Ukai, Yasuhiro ,  Aoki, Shigeo

IPC分类号： H01L29/784 ,  H01L29/163 ,  H01L29/161 ,  H01L29/62

CPC分类号： G02F1/1368 ,  H01L29/154 ,  H01L29/1604 ,  H01L29/432 ,  H01L29/7782 ,  H01L29/78684 ,  H01L29/78687 ,  H01L31/03765 ,  Y02E10/548

摘要： A thin film transistor having an active layer (24) formed between source and drain electrodes (14,15), a gate insulating film (25) formed in contact with the active layer (24) and a gate electrode (18) formed in contact with the gate insulating film (25), said active layer (24) being a multilayer structure of well layers made of hydrogenated amorphous silicon and barrier layers made of hydrogenated amorphous silicon carbide. The gate insulating film (25) can further be made of an amorphous silicon carbide layer having a carbon content greater than the carbon content of the active layer (24).

摘要翻译： 一种薄膜晶体管，具有形成在源极和漏极（14,15）之间的有源层（24），与有源层（24）接触形成的栅极绝缘膜（25）和接触形成的栅极电极（18） 与所述栅极绝缘膜（25）一起，所述有源层（24）是由氢化非晶硅制成的阱层和由氢化非晶碳化硅制成的阻挡层的多层结构。 栅绝缘膜（25）可以进一步由碳含量大于有源层（24）的碳含量的非晶碳化硅层制成。

公开(公告)号：EP0276002A3

公开(公告)日：1990-08-29

申请号：EP88100845.2

申请日：1988-01-21

申请人： HOSIDEN CORPORATION

发明人： Ukai, Yasuhiro ,  Aoki, Shigeo

IPC分类号： H01L29/78 ,  H01L29/161 ,  H01L29/163 ,  H01L29/62

CPC分类号： G02F1/1368 ,  H01L29/154 ,  H01L29/1604 ,  H01L29/432 ,  H01L29/7782 ,  H01L29/78684 ,  H01L29/78687 ,  H01L31/03765 ,  Y02E10/548

摘要： A thin film transistor having an active layer (19, 24) comprising amorphous silicon carbide (a-Si 1-x C x ) formed between source and drain electrodes (14,15), a gate insulating film (17) formed in contact with the active layer (19, 24) and a gate electrode (18) formed in contact with the gate insulating film (17), the active layer. The gate insulating layer (17, 23) can be made of an amorphous silicon carbide layer having a carbon content greater than the carbon content of the active layer (19, 24). The active layer (24) can further ba a laminated structure of well layers and barrier layers, both made of hydrogenated amorphous silicon carbide with different carbon content, or a laminated structure of well layers made of hydrogenated amorphous silicon and barrier layers made of hydrogenated amorphous silicon carbide.

摘要翻译： 一种薄膜晶体管，其具有在源极和漏极之间形成的包括非晶碳化硅（a-Si1-xCx）的有源层（19,24），与有源层接触形成的栅极绝缘膜（17） （19,24）以及与所述栅极绝缘膜（17）接触而形成的栅电极（18），所述有源层。 栅绝缘层17,23可以由碳含量大于有源层19,24的碳含量的非晶碳化硅层制成。 有源层（24）可以进一步包括均由具有不同碳含量的氢化非晶碳化硅制成的阱层和阻挡层的叠层结构，或者由氢化非晶硅制成的阱层和由氢化非晶碳制成的阻挡层的叠层结构 碳化硅。

公开(公告)号：EP0276002B1

公开(公告)日：1993-05-19

申请号：EP88100845.2

申请日：1988-01-21

申请人： HOSIDEN CORPORATION

发明人： Ukai, Yasuhiro ,  Aoki, Shigeo

IPC分类号： H01L29/78 ,  H01L29/161 ,  H01L29/163 ,  H01L29/62

CPC分类号： G02F1/1368 ,  H01L29/154 ,  H01L29/1604 ,  H01L29/432 ,  H01L29/7782 ,  H01L29/78684 ,  H01L29/78687 ,  H01L31/03765 ,  Y02E10/548

公开(公告)号：EP0241988A3

公开(公告)日：1988-03-02

申请号：EP87200641

申请日：1987-04-06

申请人： PHILIPS ELECTRONIC AND ASSOCIATED INDUSTRIES LIMITED ,  N.V. Philips' Gloeilampenfabrieken

发明人： Ralph, Hugh Ivor

IPC分类号： H01L29/203 ,  H01L29/163 ,  H01L29/80 ,  H01L29/78 ,  H01L27/08

CPC分类号： H01L29/7785

摘要： A high mobility p channel semiconductor device (such as a field-effect transistor) is formed suitable for operation at room temperature, for example in a circuit with an n channel device. Whereas hole modulation doping both in single heterojunction and in heterostructure quantum well devices provides a significant increase in hole mobility only at cryogenic temperatures, the present invention employs less than 5nm wide and very deep quantum wells 1 (about 0.4 eV and deeper) to reduce the effective mass of "heavy" conduction holes for motion in the plane of the quantum well 1. Hole mobilities at 300 degrees K are obtained in excess of 2.5 times those in bulk material of the same narrow bandgap semiconductor as used for the quantum well 1. In a particular example such a quantum well 1 is formed of GaAs (or GaInAs) between AlAs barrier layers 2.

公开(公告)号：EP0229672A3

公开(公告)日：1988-01-13

申请号：EP87100517

申请日：1987-01-16

申请人： NEC CORPORATION

发明人： Sone, Junichi

IPC分类号： H01L29/72 ,  H01L29/163 ,  H01L29/267

CPC分类号： H01L29/7378 ,  H01L29/161 ,  H01L29/267

摘要： The heterojunction bipolar transistor has a structure of wide band-gap transistor and comprises a collector region having an N-type GaAs layer, a base region having a P-type germanium layer formed on the N-type GaAs layer, and an emitter region having an N-type semiconductor layer of mixed crystal of silicon and germanium formed on the P-type germanium layer. The mixed crystal of the N-type semiconductor layer may have a uniform distribution of silicon or a graded distribution of silicon in which a content of silicon is zero at the surface facing the P-type germanium layer and is continuously increased with distance from the surface facing the P-type germanium layer.

公开(公告)号：EP0241988B1

公开(公告)日：1993-06-30

申请号：EP87200641.6

申请日：1987-04-06

申请人： PHILIPS ELECTRONICS UK LIMITED ,  Philips Electronics N.V.

发明人： Ralph, Hugh Ivor

IPC分类号： H01L29/203 ,  H01L29/163 ,  H01L29/80 ,  H01L29/78 ,  H01L27/08

CPC分类号： H01L29/7785

公开(公告)号：EP0276002A2

公开(公告)日：1988-07-27

申请号：EP88100845.2

申请日：1988-01-21

申请人： HOSIDEN CORPORATION

发明人： Ukai, Yasuhiro ,  Aoki, Shigeo

IPC分类号： H01L29/78 ,  H01L29/161 ,  H01L29/163 ,  H01L29/62

CPC分类号： G02F1/1368 ,  H01L29/154 ,  H01L29/1604 ,  H01L29/432 ,  H01L29/7782 ,  H01L29/78684 ,  H01L29/78687 ,  H01L31/03765 ,  Y02E10/548

摘要： A thin film transistor having an active layer (19, 24) comprising amorphous silicon carbide (a-Si 1-x C x ) formed between source and drain electrodes (14,15), a gate insulating film (17) formed in contact with the active layer (19, 24) and a gate electrode (18) formed in contact with the gate insulating film (17), the active layer.
The gate insulating layer (17, 23) can be made of an amorphous silicon carbide layer having a carbon content greater than the carbon content of the active layer (19, 24).
The active layer (24) can further ba a laminated structure of well layers and barrier layers, both made of hydrogenated amorphous silicon carbide with different carbon content, or a laminated structure of well layers made of hydrogenated amorphous silicon and barrier layers made of hydrogenated amorphous silicon carbide.

摘要翻译： 一种薄膜晶体管，具有形成在源电极和漏电极之间形成的非晶碳化硅（a-Si1-xCx）的有源层（19,24），形成为与有源层接触的栅极绝缘膜（17） （19,24）和与栅极绝缘膜（17）接触形成的栅电极（18），即有源层。 栅绝缘层（17,23）可以由碳含量大于活性层（19,24）的碳含量的非晶碳化硅层制成。 活性层（24）还可以进一步包括由具有不同碳含量的氢化非晶碳化硅制成的阱层和阻挡层的叠层结构，或由氢化非晶硅和由氢化非晶形成的阻挡层制成的阱层的层压结构 碳化硅。

公开(公告)号：EP0241988A2

公开(公告)日：1987-10-21

申请号：EP87200641.6

申请日：1987-04-06

申请人： PHILIPS ELECTRONICS UK LIMITED ,  Philips Electronics N.V.

发明人： Ralph, Hugh Ivor

IPC分类号： H01L29/203 ,  H01L29/163 ,  H01L29/80 ,  H01L29/78 ,  H01L27/08

CPC分类号： H01L29/7785

摘要： A high mobility p channel semiconductor device (such as a field-effect transistor) is formed suitable for operation at room temperature, for example in a circuit with an n channel device. Whereas hole modulation doping both in single heterojunction and in heterostructure quantum well devices provides a significant increase in hole mobility only at cryogenic temperatures, the present invention employs less than 5nm wide and very deep quantum wells 1 (about 0.4 eV and deeper) to reduce the effective mass of "heavy" conduction holes for motion in the plane of the quantum well 1. Hole mobilities at 300 degrees K are obtained in excess of 2.5 times those in bulk material of the same narrow bandgap semiconductor as used for the quantum well 1. In a particular example such a quantum well 1 is formed of GaAs (or GaInAs) between AlAs barrier layers 2.

摘要翻译： 形成适合于在室温下操作的高迁移率p沟道半导体器件（例如场效应晶体管），例如在具有n沟道器件的电路中。 尽管在单异质结和异质结构量子阱器件中的空穴调制掺杂仅在低温下仅提供空穴迁移率的显着增加，但是本发明使用小于5nm的宽和非常深的量子阱1（约0.4eV和更深）来减少 在量子阱1的平面中用于运动的“重”导电孔的有效质量。在300度K处的空穴迁移率被获得超过量子阱1所使用的相同窄带隙半导体的散装材料的2.5倍。 在一个具体实例中，这样的量子阱1由AlAs势垒层2之间的GaAs（或GaInAs）形成。