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    Hot charge-carrier transistors
    1.
    发明公开
    Hot charge-carrier transistors 失效
    热载流子晶体管

    公开(公告)号：EP0247667A1

    公开(公告)日：1987-12-02

    申请号：EP87200887.5

    申请日：1987-05-14

    申请人： PHILIPS ELECTRONICS UK LIMITED ,  Philips Electronics N.V.

    发明人： Shannon, John Martin

    IPC分类号： H01L29/76 ,  H01L29/08 ,  H01L29/203 ,  H01L29/10

    CPC分类号： H01L29/205 ,  H01L29/7606

    摘要： Current flow through the base region (3) of a hot charge-carrier transistor is by hot majority charge-carriers (i.e. hot electrons for a hot electron transistor) which are collected at a base-collector barrier (4). This barrier may be formed by a semiconductor region (4) which is doped with impurity of the opposite conductivity type ( p type for a hot electron transistor) and which is sufficiently thin as to form a bulk unipolar diode with an adjacent part of the base region (3). In accordance with the invention, one or more layers (5 a ) of wider-bandgap semiconductor material (for example, gallium aluminium arsenide) are present within the collector region (for example, of gallium arsenide) to form one or possibly even a series of heterojunctions (51) each providing an electric field which retards the hot charge-carriers in the collector region (5, 5 a , 5 b , 6). The retarding field cools the hot charge-carriers after collection so reducing a tendency to create electron-hole pairs by ionization. By spacing the first heterojunction (51) from the base-collector barrier (4), a high collector field is maintained in the narrow bandgap material (5) in the immediate vicinity of the potential maximum of the collector barrier (4) so maintaining a high collection efficiency.

    摘要翻译： 通过热电荷载流子晶体管的基极区（3）的电流流过在基极集电极阻挡层（4）处收集的热的多数电荷载流子（即热电子晶体管的热电子）。 该阻挡层可以由掺杂有相反导电类型（p型用于热电子晶体管）的杂质的半导体区域（4）形成，并且该半导体区域足够薄以致于与基底的相邻部分形成块状单极二极管 区域（3）。 根据本发明，在集电极区（例如砷化镓）内存在一个或多个宽带隙半导体材料层（5a）（例如砷化镓铝），以形成一个或多个甚至一系列 每个异质结提供阻止集电极区（5,5a，5b，6）中的热电荷载流子的电场。 阻滞场在收集后冷却热电荷载体，从而减少了通过电离产生电子 - 空穴对的趋势。 通过将第一异质结（51）与基极 - 集电极阻挡层（4）隔开，在紧邻集电极阻挡层（4）的电位最大值的窄带隙材料（5）中保持高的集电极电场， 收集效率高。

    Group III-V compound semiconductor device including a group IV element doped region
    2.
    发明公开
    Group III-V compound semiconductor device including a group IV element doped region 失效
    III-V族化合物半导体器件，其中包括IV族元素掺杂区域

    公开(公告)号：EP0585003A3

    公开(公告)日：1996-01-31

    申请号：EP93306352.1

    申请日：1993-08-11

    申请人： AT&T Corp.

    发明人： Kopf, Rose Fasano ,  Schubert, Erdmann Frederick

    IPC分类号： H01L29/207 ,  H01L29/36 ,  H01L29/203 ,  H01L21/203

    CPC分类号： H01L29/861 ,  H01L21/02392 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02507 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02631 ,  H01L29/155 ,  H01L29/207

    摘要： This invention embodies devices comprising Group III-V compound semiconductors in which p or n or both p and n regions are formed by a superlattice (13, 14) selectively doped with an amphoteric Group IV element dopant (23) selected from carbon, germanium and silicon. The superlattice includes a plurality of periods (20), each including two layers (21, 22). Depending on the conductivity type, only one of the layers in the periods forming the superlattice region of said type of conductivity is selectively doped with said dopant, leaving the other layer in these periods undoped. The superlattice is formed by Molecular Beam Epitaxy technique, and the dopant is incorporated into respective layers by delta-doping as in a sheet centrally deposited between monolayers forming the respective layers of the period. Each period includes 5 to 15 monolayers deposited in the two layers in a numerical ratio corresponding to a cation compositional ratio in the compound semiconductor. Low growth temperatures, e.g. ranging from 410 to 450°C lead to mirror-like surfaces. For a compound semiconductor Ga 0.47 In 0.53 As, the GaAs/InAs ordered superlattices with eight monolayers per period are grown in a ratio of 0.47/0.53. At free carrier concentrations of 10¹⁶cm⁻³, carrier mobilities of 200 and 2300 cm² /Vs for p-type and n-type are obtained with carbon as the amphoteric dopant.

    Heterojunction bipolar transistor with ballistic operation
    3.
    发明公开
    Heterojunction bipolar transistor with ballistic operation 失效
    BipolarerHeteroübergangs-Transistor mit ballistischem Betrieb。

    公开(公告)号：EP0273363A2

    公开(公告)日：1988-07-06

    申请号：EP87119044.3

    申请日：1987-12-22

    申请人： NEC CORPORATION

    发明人： Honjo, Kazuhiko c/o NEC Corporation ,  Tanaka, Shin-ichi c/o NEC Corporation

    IPC分类号： H01L29/72 ,  H01L29/205 ,  H01L29/203 ,  H01L29/10 ,  H01L29/08

    CPC分类号： H01L29/7371 ,  H01L29/205

    摘要： For improvement in operation speed, there is provided a heterojunction bipolar transistor comprising, a) an emitter region (27) formed of a first semiconductor material of a first conductivity type, b) a base region (24) formed of a second semiconductor material of a second conductivity type opposite to the first conductivity type and forming a first junction together with the emitter region, and c) a collector region (23) formed of a third semiconductor material of the first conductivity type and forming a second junction together with the base region, the heterojunction bipolar transistor has a plurality of abrupt potential discontinuities including first and second abrupt potential discontinuities produced in succession to provide kinetic energies to a carrier injected from the emitter region, respectively, and the first abrupt potential discontinuity is produced at one of the first and second junctions, thereby allowing the carrier to move over a distance longer than a linear free path of the carrier in the ballistic manner.

    摘要翻译： 为了提高操作速度，提供了一种异质结双极晶体管，它包括a）由第一导电类型的第一半导体材料形成的发射极区域（27），b）由第二半导体材料形成的基极区域 与第一导电类型相反的第二导电类型并与发射极区一起形成第一结，以及c）由第一导电类型的第三半导体材料形成的集电极区（23），并与基底一起形成第二结 区域中，异质结双极晶体管具有多个突变电位不连续性，其包括分别产生的第一和第二突变电位不连续性，以向从发射极区域注入的载流子提供动能，并且第一突变电位不连续性 第一和第二结，从而允许载体移动超过线性自由的距离 航空母舰的弹道方式。

    Heterojunction semiconductor device
    4.
    发明公开
    Heterojunction semiconductor device 失效
    异步半导体器件

    公开(公告)号：EP0238406A3

    公开(公告)日：1987-11-19

    申请号：EP87400571

    申请日：1987-03-13

    申请人： FUJITSU LIMITED

    发明人： Awano, Yuji Haishiti Omotasando 312

    IPC分类号： H01L29/76 ,  H01L29/203

    CPC分类号： H01L29/155 ,  B82Y10/00 ,  B82Y30/00 ,  H01L29/7606 ,  Y10S977/761 ,  Y10S977/936 ,  Y10S977/961

    摘要： A heterojunction semiconductor device comprises an unipolar transistor comprising, a collector layer (3), a base layer (5), a collector side barrier layer (4) provided between said collector layer (3) and base layer (5), an emitter layer (8), and an emitter side barrier layer (7) provided between said base layer (5) and emitter layer (8) and having a thickness for tunneling a carrier from said emitter (8) and base (5) layers, said carrier being injected into the base layer (5) according to the application of a predetermined voltage between said emitter and base, said base layer (5) having a superlattice means (6), comprising a plurality of thin barrier layers (6B) and thin well layers (6W) for forming a mini-band through which the injected carrier can move and a mini-band gap with which the injected carrier collides.

    Resonant-tunneling transistor
    9.
    发明公开
    Resonant-tunneling transistor 失效
    谐振隧道晶体管

    公开(公告)号：EP0226383A3

    公开(公告)日：1987-12-23

    申请号：EP86309383

    申请日：1986-12-02

    申请人： FUJITSU LIMITED

    发明人： Yokohama, Naoki ,  Imamura, Kenichi

    IPC分类号： H01L29/72 ,  H01L29/203

    CPC分类号： B82Y10/00 ,  B82Y30/00 ,  H01L29/0895 ,  H01L29/7376

    摘要： A resonant-tunneling heterojunction bipolar transistor (RHBT) device, having a superlattice structure and a PN junction, includes an emitter layer (17), a base layer (14), a collector layer (13) operatively facing the base layer to form a PN junction at the face between the base layer and the collector layer, and a superlattice structure (16) including at least one quantum well defining a sub-band of energy at which carriers resonant-tunnel therethrough, formed at least in the emitter layer and operatively facing the base layer. The RHBT has differential negative resistance characteristics for realizing a variety of logic circuits and includes an electron resonance and a positive hole resonance, for which the generation condition is changeable in response to a mole fraction of material of the emitter layer. Such an RHBT, unlike a prior RHET, can be made to operate satisfactorily at normal ambient temperatures with adequate current gain.

    High mobility semiconductor devices
    10.
    发明公开
    High mobility semiconductor devices 失效
    Halbleiteranordnungen mit hoher Beweglichkeit。

    公开(公告)号：EP0241988A2

    公开(公告)日：1987-10-21

    申请号：EP87200641.6

    申请日：1987-04-06

    申请人： PHILIPS ELECTRONICS UK LIMITED ,  Philips Electronics N.V.

    发明人： Ralph, Hugh Ivor

    IPC分类号： H01L29/203 ,  H01L29/163 ,  H01L29/80 ,  H01L29/78 ,  H01L27/08

    CPC分类号： H01L29/7785

    摘要： A high mobility p channel semiconductor device (such as a field-effect transistor) is formed suitable for operation at room temperature, for example in a circuit with an n channel device. Whereas hole modulation doping both in single heterojunction and in heterostructure quantum well devices provides a significant increase in hole mobility only at cryogenic temperatures, the present invention employs less than 5nm wide and very deep quantum wells 1 (about 0.4 eV and deeper) to reduce the effective mass of "heavy" conduction holes for motion in the plane of the quantum well 1. Hole mobilities at 300 degrees K are obtained in excess of 2.5 times those in bulk material of the same narrow bandgap semiconductor as used for the quantum well 1. In a particular example such a quantum well 1 is formed of GaAs (or GaInAs) between AlAs barrier layers 2.

    摘要翻译： 形成适合于在室温下操作的高迁移率p沟道半导体器件（例如场效应晶体管），例如在具有n沟道器件的电路中。 尽管在单异质结和异质结构量子阱器件中的空穴调制掺杂仅在低温下仅提供空穴迁移率的显着增加，但是本发明使用小于5nm的宽和非常深的量子阱1（约0.4eV和更深）来减少 在量子阱1的平面中用于运动的“重”导电孔的有效质量。在300度K处的空穴迁移率被获得超过量子阱1所使用的相同窄带隙半导体的散装材料的2.5倍。 在一个具体实例中，这样的量子阱1由AlAs势垒层2之间的GaAs（或GaInAs）形成。